Patents by Inventor Michiaki Sano

Michiaki Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10083982
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 25, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keisuke Shigemura, Junichi Ariyoshi, Masanori Tsutsumi, Michiaki Sano, Yanli Zhang, Raghuveer S. Makala
  • Patent number: 10083877
    Abstract: A two-dimensional array of vertical field effect transistors is provided, which includes a first-tier structure and a second-tier structure. The first-tier structure includes a laterally alternating sequence of semiconductor rail structures and first dielectric isolation rails that alternates along a first horizontal direction. A first gate dielectric and a first gate electrode that laterally extend along a second horizontal direction are disposed between each neighboring pair of a semiconductor rail structure and a first dielectric isolation rail. The second-tier structure includes a laterally alternating sequence of composite rail structures and second dielectric isolation rails that alternates along the second horizontal direction. Each of the composite rail structures includes a laterally alternating plurality of semiconductor pillar structures and dielectric pillar structures.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 25, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Michiaki Sano, Tetsuya Yamada
  • Publication number: 20180247954
    Abstract: A semiconductor device includes a silicon surface, a titanium silicide layer contacting the silicon surface, a first titanium nitride layer located over the titanium silicide layer, a titanium oxynitride layer contacting the first titanium nitride layer, a second titanium nitride layer contacting the titanium oxynitride layer, and a metal fill layer located over the second titanium nitride layer.
    Type: Application
    Filed: June 8, 2017
    Publication date: August 30, 2018
    Inventors: Fumitaka Amano, Kensuke Ishikawa, Shinya Inoue, Michiaki Sano
  • Publication number: 20180247976
    Abstract: A method is provided that includes forming a dielectric material and a first sacrificial material above a substrate, forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material, forming a first hole in the second sacrificial material, the first hole disposed in a first direction, forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole, forming a second hole in the second sacrificial material, forming a second portion of the nonvolatile memory material on a sidewall of the second hole, forming a local bit line in the second hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.
    Type: Application
    Filed: February 28, 2017
    Publication date: August 30, 2018
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Jongsun Sel, Daewung Kang, Michiaki Sano, Yohei Yamada, Mitsuteru Mushiga, Tuan Pham
  • Publication number: 20180158873
    Abstract: A wedge-shaped contact region can be employed to provide electrical contacts to multiple electrically conductive layers in a three-dimensional device structure. A cavity including a generally wedge-shaped region and a primary region is formed in a dielectric matrix layer over a support structure. An alternating stack of insulating layers and electrically conductive layers is formed by a series of conformal deposition processes in the cavity and over the dielectric matrix layer. The alternating stack can be planarized employing the top surface of the dielectric matrix layer as a stopping layer. A tip portion of each electrically conductive layer within remaining portions of the alternating stack is laterally offset from the tip of the generally wedge-shaped region by a respective lateral offset distance along a lateral protrusion direction. Contact via structures can be formed on the tip portions of the electrically conductive layers to provide electrical contact.
    Type: Application
    Filed: December 2, 2016
    Publication date: June 7, 2018
    Inventors: Michiaki SANO, Zhen CHEN, Tetsuya YAMADA, Akira NAKADA, Yasuke ODA, Manabu HAYASHI, Shigenori SATO
  • Publication number: 20180138194
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.
    Type: Application
    Filed: April 25, 2017
    Publication date: May 17, 2018
    Inventors: Keisuke SHIGEMURA, Junichi ARIYOSHI, Masanori TSUTSUMI, Michiaki SANO, Yanli ZHANG, Raghuveer S. MAKALA
  • Patent number: 9911790
    Abstract: A plurality of alternating stacks laterally spaced apart by line trenches is provided over a substrate. Each alternating stack includes respective word lines and respective dielectric material layers. An alternating sequence of vertical bit lines and inter-bit-line cavities is formed within each of the line trenches. Resistive memory material layers including resistive memory elements are provided at intersection regions between the word lines and the vertical bit lines. Air gaps are formed by removing at least a predominant portion of each of the dielectric material layers selective to the word lines, the vertical bit lines, and the resistive memory material layers, thereby forming a plurality of alternating stacks of the word lines and air gaps. A dielectric isolation layer including vertically-extending voids can be formed over the plurality of alternating stacks in the inter-bit-line cavities.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: March 6, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Seiji Shimabukuro, Michiaki Sano, Kan Fujiwara
  • Patent number: 9728499
    Abstract: A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: August 8, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Seiji Shimabukuro, Hiroaki Iuchi, Michiaki Sano, Naoki Takeguchi
  • Patent number: 9673304
    Abstract: A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 6, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Michiaki Sano, Akira Nakada, Tetsuya Yamada, Manabu Hayashi, Takashi Matsubara, Sung Tae Lee, Akio Nishida
  • Patent number: 9666799
    Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: May 30, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohito Yanagida, Cheng Feng, Michiaki Sano, Akira Nakada, Steven J. Radigan, Eiji Hayashi
  • Patent number: 9620712
    Abstract: An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: April 11, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Eiji Hayashi, Naohito Yanagida, Michiaki Sano, Akira Nakada
  • Patent number: 9601502
    Abstract: A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the semiconductor substrate. An alternating stack of insulating layers and sacrificial material layers are formed over the semiconductor substrate, and memory stack structures are formed therethrough. Contact openings extending to sacrificial material layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. Electrically conductive via structures extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liners.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: March 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Michiaki Sano, Keisuke Izumi
  • Patent number: 9576967
    Abstract: Memory openings and support openings are formed through an alternating stack of insulating layers and spacer material layers over a semiconductor substrate. Deposition of a semiconductor material in the support openings during formation of epitaxial channel portions in the memory openings is prevented by Portions of the semiconductor substrate that underlie the support openings are converted into impurity-doped semiconductor material portions. During selective growth of epitaxial channel portions from the semiconductor substrate within the memory openings, growth of a semiconductor material in the support openings is suppressed due to the impurity species in the impurity-doped semiconductor material portions. Memory stack structures and support pillar structures are subsequently formed over the epitaxial channel portions and in the support openings, respectively.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 21, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hajime Kimura, Seiji Shimabukuro, Shuji Minagawa, Michiaki Sano, Masanori Tsutsumi
  • Patent number: 9524901
    Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of alternating sacrificial layers and insulating layers located over a major surface of a substrate. A contact mask having contact mask openings is provided over the stack, and a first over mask having first over mask openings is provided over the contact mask. A subset of the contact mask openings is substantially aligned with the first over mask openings. Contact openings are formed through the stack, wherein each of the contact openings extends substantially perpendicular to the major surface of the substrate to a respective one of the sacrificial layers. A plurality of electrically conductive via contacts is formed in the plurality of the contact openings.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: December 20, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keisuke Izumi, Michiaki Sano, Hiroshi Sasaki
  • Publication number: 20160322374
    Abstract: A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the semiconductor substrate. An alternating stack of insulating layers and sacrificial material layers are formed over the semiconductor substrate, and memory stack structures are formed therethrough. Contact openings extending to sacrificial material layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. Electrically conductive via structures extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liners.
    Type: Application
    Filed: July 15, 2016
    Publication date: November 3, 2016
    Inventors: Michiaki SANO, Keisuke IZUMI
  • Patent number: 9437543
    Abstract: A contact via cavity can be filled with a lower structure and an upper structure. The lower structure can be a conductive structure that is formed by depositing a conformal conductive material, and subsequently removing an upper portion of the conformal conductive material. A disposable material portion can be formed at a bottom of the cavity to protect the bottom portion of the conformal conductive layer during removal of the upper portion. After removal of the disposable material, at least one conductive material can fill the remainder of the cavity to form the upper structure. The upper structure and the lower structure collectively constitute a contact via structure. Alternatively, the lower structure can be a dielectric spacer with an opening therethrough. The upper structure can be a conductive structure that extends through the dielectric spacer, and provides an electrically conductive vertical connection.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: September 6, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Akira Nakada, Michiaki Sano, Motoki Kawasaki, Sung Tae Lee
  • Patent number: 9412753
    Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of a plurality of alternating sacrificial layers and insulator layers located over a major surface of a substrate. A contact mask with at least one contact mask opening and at least one first terrace mask opening is provided over the stack, where the at least one first terrace mask opening is larger than the at least one contact mask opening. At least one first contact opening and at least one first terrace opening are simultaneously formed extending substantially perpendicular to the major surface of the substrate through the stack to a first sacrificial layer by etching a portion of the stack through the at least one contact mask opening and the at least one first terrace mask opening. A first electrically conductive via contact is deposited in the at least one first contact opening.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 9, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keisuke Izumi, Michiaki Sano, Hiroshi Sasaki
  • Publication number: 20160218059
    Abstract: A contact via cavity can be filled with a lower structure and an upper structure. The lower structure can be a conductive structure that is formed by depositing a conformal conductive material, and subsequently removing an upper portion of the conformal conductive material. A disposable material portion can be formed at a bottom of the cavity to protect the bottom portion of the conformal conductive layer during removal of the upper portion. After removal of the disposable material, at least one conductive material can fill the remainder of the cavity to form the upper structure. The upper structure and the lower structure collectively constitute a contact via structure. Alternatively, the lower structure can be a dielectric spacer with an opening therethrough. The upper structure can be a conductive structure that extends through the dielectric spacer, and provides an electrically conductive vertical connection.
    Type: Application
    Filed: January 22, 2015
    Publication date: July 28, 2016
    Inventors: Akira NAKADA, Michiaki SANO, Motoki KAWASAKI, Sung Tae LEE
  • Patent number: 9401309
    Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: July 26, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keisuke Izumi, Naohito Yanagida, Michiaki Sano, Takehiro Yamazaki, Hiroaki Iuchi, Akio Yanai, Genta Mizuno, Minoru Yamaguchi
  • Patent number: 9368601
    Abstract: A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: June 14, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Michiaki Sano, Kensuke Yamaguchi, Akira Nakada, Naohito Yanagida