Patents by Inventor Mike Brooks

Mike Brooks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6911355
    Abstract: A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: June 28, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Mike Brooks
  • Patent number: 6891248
    Abstract: A semiconductor component includes a semiconductor die, and an on board capacitor on the die for filtering transient voltages, spurious signals and power supply noise in signals transmitted to the die. The capacitor includes a first electrode in electrical communication with a first terminal contact for the component, and a second electrode in electrical communication with a second terminal contact for the component. The electrodes are separated by a dielectric layer and protected by an outer protective layer of the component. The capacitor can be fabricated using redistribution layers on a wafer containing multiple dice. The component can be used to construct systems such as multi chip packages and multi chip modules.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: May 10, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Mike Brooks
  • Publication number: 20040238957
    Abstract: A semiconductor component includes a semiconductor die, and an on board capacitor on the die for filtering transient voltages, spurious signals and power supply noise in signals transmitted to the die. The capacitor includes a first electrode in electrical communication with a first terminal contact for the component, and a second electrode in electrical communication with a second terminal contact for the component. The electrodes are separated by a dielectric layer and protected by an outer protective layer of the component. The capacitor can be fabricated using redistribution layers on a wafer containing multiple dice. The component can be used to construct systems such as multi chip packages and multi chip modules.
    Type: Application
    Filed: July 7, 2004
    Publication date: December 2, 2004
    Inventors: Salman Akram, Mike Brooks
  • Publication number: 20040227218
    Abstract: A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit.
    Type: Application
    Filed: June 18, 2004
    Publication date: November 18, 2004
    Inventors: Warren M. Farnworth, Alan G. Wood, Mike Brooks
  • Publication number: 20040214373
    Abstract: Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 28, 2004
    Inventors: Tongbi Jiang, J. Mike Brooks
  • Publication number: 20040188820
    Abstract: Packaged microelectronic devices and methods for assembling microelectronic devices are disclosed herein. In one embodiment, a method of assembling a microelectronic device having a die and an interposer substrate includes depositing a solder ball onto a ball-pad on the interposer substrate and molding a compound to form a casing around at least a portion of the die and the solder ball. The method can further include forming a first cover over a first surface of the interposer substrate with the compound and forming a second cover over a second surface opposite the first surface of the interposer substrate with the compound. The first cover can have a first volume and a first surface area and the second cover can have a second volume and a second surface area. The first and second volumes and the first and second surface areas can be at least approximately equal.
    Type: Application
    Filed: April 5, 2004
    Publication date: September 30, 2004
    Inventors: David J. Corisis, Mike Brooks
  • Publication number: 20040173889
    Abstract: A computer system, a printed circuit board assembly, and a multiple die semiconductor assembly are provided comprising first and second semiconductor dies and an intermediate substrate. The first semiconductor die defines a first active surface including at least one conductive bond pad. The second semiconductor die defines a second active surface including at least one conductive bond pad. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The first semiconductor die is electrically coupled to the intermediate substrate by at least one topographic contact extending from the first active surface to the first surface of the intermediate substrate. The intermediate substrate defines a passage there through.
    Type: Application
    Filed: March 9, 2004
    Publication date: September 9, 2004
    Inventors: Salman Akram, Mike Brooks
  • Publication number: 20040139604
    Abstract: A technique is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a holder or shell. The holder is positioned over a support region in the receiving socket. A manual actuator is pressed into the holder to eject the device from the holder and to install the device in the support. The holder may be configured to hold a single device, or multiple devices aligned in slots defined by partitions. A multi-device tray may be provided for indexing devices toward an ejection slot, through which the devices are installed by manual actuation of an ejecting actuator. The technique provides protection for the device prior to and during installation, and facilitates manual installation of such devices without requiring direct hand contact with the device either prior to or during installation.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 22, 2004
    Inventors: Larry Kinsman, Mike Brooks, Warren M. Farnworth, Walter Moden, Terry R. Lee
  • Publication number: 20040140545
    Abstract: A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit.
    Type: Application
    Filed: January 9, 2004
    Publication date: July 22, 2004
    Inventors: Warren M. Farnworth, Alan G. Wood, Mike Brooks
  • Publication number: 20040115865
    Abstract: A semiconductor component includes a semiconductor die, and an on board capacitor on the die for filtering transient voltages, spurious signals and power supply noise in signals transmitted to the die. The capacitor includes a first electrode in electrical communication with a first terminal contact for the component, and a second electrode in electrical communication with a second terminal contact for the component. The electrodes are separated by a dielectric layer and protected by an outer protective layer of the component. The capacitor can be fabricated using redistribution layers on a wafer containing multiple dice. The component can be used to construct systems such as multi chip packages and multi chip modules.
    Type: Application
    Filed: November 25, 2003
    Publication date: June 17, 2004
    Inventors: Salman Akram, Mike Brooks
  • Patent number: 6740545
    Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound packaging during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: May 25, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Jerrold L. King, J. Mike Brooks, Walter L. Moden
  • Patent number: 6740960
    Abstract: A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: May 25, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Mike Brooks
  • Patent number: 6740546
    Abstract: Packaged microelectronic devices and methods for assembling microelectronic devices are disclosed herein. In one embodiment, a method of assembling a microelectronic device having a die and an interposer substrate includes depositing a solder ball onto a ball-pad on the interposer substrate and molding a compound to form a casing around at least a portion of the die and the solder ball. The method can further include forming a first cover over a first surface of the interposer substrate with the compound and forming a second cover over a second surface opposite the first surface of the interposer substrate with the compound. The first cover can have a first volume and a first surface area and the second cover can have a second volume and a second surface area. The first and second volumes and the first and second surface areas can be at least approximately equal.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: May 25, 2004
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Mike Brooks
  • Patent number: 6699734
    Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: March 2, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Schoenfeld, Manny K. F. Ma, Larry D. Kinsman, J. Mike Brooks, Timothy J. Allen
  • Publication number: 20040038447
    Abstract: Packaged microelectronic devices and methods for assembling microelectronic devices are disclosed herein. In one embodiment, a method of assembling a microelectronic device having a die and an interposer substrate includes depositing a solder ball onto a ball-pad on the interposer substrate and molding a compound to form a casing around at least a portion of the die and the solder ball. The method can further include forming a first cover over a first surface of the interposer substrate with the compound and forming a second cover over a second surface opposite the first surface of the interposer substrate with the compound. The first cover can have a first volume and a first surface area and the second cover can have a second volume and a second surface area. The first and second volumes and the first and second surface areas can be at least approximately equal.
    Type: Application
    Filed: August 21, 2002
    Publication date: February 26, 2004
    Inventors: David J. Corisis, Mike Brooks
  • Publication number: 20040036157
    Abstract: A semiconductor component includes a semiconductor die, and an on board capacitor on the die for filtering transient voltages, spurious signals and power supply noise in signals transmitted to the die. The capacitor includes a first electrode in electrical communication with a first terminal contact for the component, and a second electrode in electrical communication with a second terminal contact for the component. The electrodes are separated by a dielectric layer and protected by an outer protective layer of the component. The capacitor can be fabricated using redistribution layers on a wafer containing multiple dice. The component can be used to construct systems such as multi chip packages and multi chip modules.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 26, 2004
    Inventors: Salman Akram, Mike Brooks
  • Patent number: 6681480
    Abstract: A technique is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a holder or shell. The holder is positioned over a support region in the receiving socket. A manual actuator is pressed into the holder to eject the device from the holder and to install the device in the support. The holder may be configured to hold a single device, or multiple devices aligned in slots defined by partitions. A multi-device tray may be provided for indexing devices toward an ejection slot, through which the devices are installed by manual actuation of an ejecting actuator. The technique provides protection for the device prior to and during installation, and facilitates manual installation of such devices without requiring direct hand contact with the device either prior to or during installation.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: January 27, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Larry Kinsman, Mike Brooks, Warren M. Farnworth, Walter Moden, Terry Lee
  • Patent number: 6614104
    Abstract: A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: September 2, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Mike Brooks
  • Patent number: 6600215
    Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: July 29, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Schoenfeld, Manny K. F. Ma, Larry D. Kinsman, J. Mike Brooks, Timothy J. Allen
  • Publication number: 20030113953
    Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.
    Type: Application
    Filed: January 31, 2003
    Publication date: June 19, 2003
    Inventors: Aaron Schoenfeld, Manny K.F. Ma, Larry D. Kinsman, J. Mike Brooks, Timothy J. Allen