Abstract: A semiconductor package and method for fabricating the package are provided. The package includes a semiconductor die and a heat sink in thermal communication with the die. The heat sink includes one or more pad structures adapted to form bonded connections, and thermal paths to contacts on a substrate. The method includes forming multiple heat sinks on a frame similar to a lead frame, and etching or stamping the pad structures on the heat sink. The frame can then be attached to a leadframe containing encapsulated dice, and the assembly singulated to form separate packages. The packages can be used to form electronic assemblies such as circuit board assemblies and multi chip modules.

Abstract: A semiconductor package and method for fabricating the package are provided. The package includes a semiconductor die and a heat sink in thermal communication with the die. The heat sink includes one or more pad structures adapted to form bonded connections, and thermal paths to contacts on a substrate. The method includes forming multiple heat sinks on a frame similar to a lead frame, and etching or stamping the pad structures on the heat sink. The frame can then be attached to a leadframe containing encapsulated dice, and the assembly singulated to form separate packages. The packages can be used to form electronic assemblies such as circuit board assemblies and multi chip modules.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract: A method of forming a semiconductor memory device comprises the steps of providing a semiconductor die, forming a temporary protective material over a surface of the die, and attaching the die to a first lead frame portion. Next, a protective material is contacted with a second lead frame portion and, subsequently, the second lead frame portion is electrically connected with the second lead frame portion with bond pads on the first surface of the die with bond wires. Subsequent to electrically connecting the die and the second lead frame portion the protective material is removed.

Abstract: A semiconductor package and a method for fabricating the package are provided. The package includes multiple substrates in a stacked configuration, each having a semiconductor die mounted thereon. Each substrate includes matching patterns of external contacts and contact pads formed on opposing sides of the substrate, and interconnected by interlevel conductors through the substrate. In the package, the external contacts on a first substrate are bonded to the contact pads on an adjacent second substrate, so that all of the dice in the package are interconnected. The fabrication process includes forming multiple substrates on a panel, mounting the dice to the substrates, stacking and bonding the panels to one another, and then separating the substrates from the stacked panels to form the packages.

Abstract: A semiconductor package and a method of fabrication are provided. The package includes multiple semiconductor dice contained in a housing, and mounted on edge to a substrate. Each die includes a polymer interconnect which attaches to a face of the die, and wraps around an end (or side) of the die. The polymer interconnect includes a flexible polymer tape with patterns of conductors. The conductors include microbumps for bonding to the die bond pads, and edge contacts for electrical connection to mating contacts on the substrate. The package also includes a force applying mechanism for biasing the dice against the substrate. In alternate embodiments, the polymer interconnect includes resilient edge contacts, cantilevered edge contacts, or multi level edge contacts.

Abstract: A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

Abstract: An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.

Abstract: A carrier for testing an unpackaged semiconductor die is provided. The carrier comprises a base for holding the die, an interconnect for establishing a temporary electrical connection with the die, and a force applying mechanism for biasing the die and interconnect together. The base includes external contacts arranged as flat metal pads in a dense grid array and electrically connected to a pattern of contact pads. The carrier also includes a pair of slide connector members which provide an electrical p ath between the contact pads on the base and corresponding contact pads on the interconnect. The slide connector members can be formed of molded plastic or ceramic and include tine contacts that slidably engage the contact pads on the interconnect and base. The slide connector members permit the interconnect to be easily replaced for testing of different types of dice.

Abstract: A semiconductor package and method for fabricating the package are provided. The package includes a semiconductor die and a heat sink in thermal communication with the die. The heat sink includes one or more pad structures adapted to form bonded connections, and thermal paths to contacts on a substrate. The method includes forming multiple heat sinks on a frame similar to a lead frame, and etching or stamping the pad structures on the heat sink. The frame can then be attached to a leadframe containing encapsulated dice, and the assembly singulated to form separate packages. The packages can be used to form electronic assemblies such as circuit board assemblies and multi chip modules.

Abstract: A method for forming a semiconductor device comprises the steps of providing a semiconductor die having a plurality of pads thereon with at least one bond wire electrically coupled with one of the pads and providing a holder having a cavity therein. The die is placed in the cavity, then a layer of encapsulation is formed within the cavity to cover the die. Subsequently, the encapsulated die is removed from the cavity.

Abstract: A semiconductor package and a method for fabricating the package are provided. The package includes multiple substrates in a stacked configuration, each having a semiconductor die mounted thereon. Each substrate includes matching patterns of external contacts and contact pads formed on opposing sides of the substrate, and interconnected by interlevel conductors through the substrate. In the package, the external contacts on a first substrate are bonded to the contact pads on an adjacent second substrate, so that all of the dice in the package are interconnected. The fabrication process includes forming multiple substrates on a panel, mounting the dice to the substrates, stacking and bonding the panels to one another, and then separating the substrates from the stacked panels to form the packages.

Abstract: A semiconductor package and a method of fabrication are provided. The package includes multiple semiconductor dice contained in a housing, and mounted on edge to a substrate. Each die includes a polymer interconnect which attaches to a face of the die, and wraps around an end (or side) of the die. The polymer interconnect includes a flexible polymer tape with patterns of conductors. The conductors include microbumps for bonding to the die bond pads, and edge contacts for electrical connection to mating contacts on the substrate. The package also includes a force applying mechanism for biasing the dice against the substrate. In alternate embodiments, the polymer interconnect includes resilient edge contacts, cantilevered edge contacts, or multi level edge contacts.

Abstract: An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.