Patents by Inventor Mikihiko Nishitani

Mikihiko Nishitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100096986
    Abstract: The present invention improves discharge characteristics of a protective layer in order to provide a PDP that exhibits excellent display performance even if the PDP is of a fine-cell structure. The present invention also provides a manufacturing method for the PDP. In particular, a protective layer 8 is composed of an MgO film layer 81 and an MgO particle layer 82 that is made of MgO particles 16. The MgO particles 16 are formed by burning an MgO precursor and satisfy that a/b?1, where a denotes a spectrum integral value in a wavelength region of a CL spectrum from 200 nm to 300 nm, exclusive of 300 nm, and b denotes a spectrum integral value in a wavelength region of the CL spectrum from 300 nm to 550 nm, exclusive of 550 nm.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 22, 2010
    Inventors: Takuji Tsujita, Yusuke Fukui, Masaharu Terauchi, Mikihiko Nishitani, Michiko Okafuji, Kaname Mizokami
  • Patent number: 7692864
    Abstract: A crystallization method includes wavefront-dividing an incident light beam into a plurality of light beams, condensing the wavefront-divided light beams in a corresponding phase shift portion of a phase shift mask or in the vicinity of the phase shift portion to form a light beam having an light intensity distribution of an inverse peak pattern in which a light intensity is minimum in a point corresponding to the phase shift portion of the phase shift mask, and irradiating a polycrystalline semiconductor film or an amorphous semiconductor film with the light beam having the light intensity distribution to produce a crystallized semiconductor film.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: April 6, 2010
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Publication number: 20100039033
    Abstract: A plasma display panel in which a first substrate having a protective layer formed thereon opposes a second substrate across a discharge space, with the substrates being sealed around a perimeter thereof. At a surface of the protective layer, first and second materials of different electron emission properties are exposed to the discharge space, with at least one of the materials existing in a dispersed state. The first and second materials may be first and second crystals, and the second crystal may be dispersed throughout the first crystal.
    Type: Application
    Filed: January 16, 2008
    Publication date: February 18, 2010
    Inventors: Yukihiro Morita, Masatoshi Kitagawa, Kiichiro Oishi, Mikihiko Nishitani
  • Patent number: 7608891
    Abstract: A thin film transistor includes a one conductive type semiconductor layer (11); a source region (12) and a drain region (13) which are separately provided in the semiconductor layer; and a gate electrode (14) provided above or below the semiconductor layer with an insulating film interposed therebetween, wherein the width (Ws) of the junction face between the source region and the channel (16) which is provided between the source region and drain region, is different from the width (Wd) of the junction face between the above channel region and the drain region.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: October 27, 2009
    Assignee: Kabushiki Kaisha Ekisho Sentan Gijutsu Kaihatsu Center
    Inventors: Masato Hiramatsu, Masakiyo Matsumura, Mikihiko Nishitani, Yoshinobu Kimura, Yoshitaka Yamamoto
  • Patent number: 7583026
    Abstract: In the plasma display panel of the present invention, a protective layer covers a dielectric layer covering electrodes in discharge cells and faces a discharge space filled with a discharge gas. Here, the discharge gas includes at least one selected from the group consisting of Xe and Kr. In the protective layer, an electron band including at least electrons having energy level of 4 eV or less below a vacuum level is formed within a forbidden band in energy bands.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: September 1, 2009
    Assignee: Panasonic Corporation
    Inventors: Mikihiko Nishitani, Masaharu Terauchi, Yukihiro Morita, Shinichi Yamamoto, Masatoshi Kitagawa
  • Patent number: 7573200
    Abstract: An object of the present invention is to reduce power consumption in a plasma display panel (PDP) by reducing the discharge firing voltage, while suppressing the occurrence of discharge variability when the PDP is driven, as well as ensuring the wall-charge holding performance of a protective film surface. To achieve this, a front panel of a PDP of the present invention has a catalyst layer dispersed on a surface of display electrodes formed in stripes on one side of a glass substrate, and needle crystals composed of graphite formed to stand upright on the catalyst layer. The needle crystals form a phase-separated structure with the materials of a dielectric film and a protective film.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: August 11, 2009
    Assignee: Panasonic Corporation
    Inventors: Shinichi Yamamoto, Mikihiko Nishitani, Yukihiro Morita
  • Patent number: 7572335
    Abstract: A crystallization apparatus includes an illumination system which illuminates a phase-shift mask and an image-forming optical system arranged in an optical path between the phase-shift mask and a semiconductor film. The semiconductor film is irradiated with a light beam having a light intensity distribution of inverted peak patterns whose light intensity is the lowest in portions corresponding to phase shift sections to form a crystallized semiconductor film. The image-forming optical system is located to optically conjugate the phase-shift mask and the semiconductor film and has an aberration corresponding to the given wavelength range to form a light intensity distribution of inverted peak patterns with no swell of intensity in the middle portion.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: August 11, 2009
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Publication number: 20090180190
    Abstract: A crystallization method includes wavefront-dividing an incident light beam into a plurality of light beams, condensing the wavefront-divided light beams in a corresponding phase shift portion of a phase shift mask or in the vicinity of the phase shift portion to form a light beam having an light intensity distribution of an inverse peak pattern in which a light intensity is minimum in a point corresponding to the phase shift portion of the phase shift mask, and irradiating a polycrystalline semiconductor film or an amorphous semiconductor film with the light beam having the light intensity distribution to produce a crystallized semiconductor film.
    Type: Application
    Filed: March 13, 2009
    Publication date: July 16, 2009
    Inventors: Yukio TANIGUCHI, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Publication number: 20090181483
    Abstract: A crystallization method includes wavefront-dividing an incident light beam into a plurality of light beams, condensing the wavefront-divided light beams in a corresponding phase shift portion of a phase shift mask or in the vicinity of the phase shift portion to form a light beam having an light intensity distribution of an inverse peak pattern in which a light intensity is minimum in a point corresponding to the phase shift portion of the phase shift mask, and irradiating a polycrystalline semiconductor film or an amorphous semiconductor film with the light beam having the light intensity distribution to produce a crystallized semiconductor film.
    Type: Application
    Filed: March 13, 2009
    Publication date: July 16, 2009
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Publication number: 20090167176
    Abstract: A PDP can be driven at low voltage while having a charge retention property in a protection layer, and has favorable image display properties. Additionally, the PDP prevents the occurrence of discharge delay and realizes high-quality image display by performing favorable high-speed driving in a high definition PDP. To achieve this, a surface layer (8) is formed to a film thickness of 1 ?m in an oxygen atmosphere having an oxygen partial pressure of 0.025 Pa or more, the surface layer (8) is provided on a face of a dielectric layer (7) on a discharge space side. Furthermore, MgO particles (16) are dispersed on a surface of the surface layer (8). The surface layer (8) has the effects of protecting the dielectric layer (7) from ion bombardment during discharge, reducing the firing voltage, and preventing excessive electron loss. Also, the MgO particles (16) have a high initial electron emission property.
    Type: Application
    Filed: April 27, 2007
    Publication date: July 2, 2009
    Inventors: Yusuke Fukui, Takuji Tsujita, Jun Hashimoto, Hikaru Nishitani, Masaharu Terauchi, Mikihiko Nishitani
  • Patent number: 7537660
    Abstract: A crystallization method includes wavefront-dividing an incident light beam into a plurality of light beams, condensing the wavefront-divided light beams in a corresponding phase shift portion of a phase shift mask or in the vicinity of the phase shift portion to form a light beam having an light intensity distribution of an inverse peak pattern in which a light intensity is minimum in a point corresponding to the phase shift portion of the phase shift mask, and irradiating a polycrystalline semiconductor film or an amorphous semiconductor film with the light beam having the light intensity distribution to produce a crystallized semiconductor film.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: May 26, 2009
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Patent number: 7505204
    Abstract: A crystallization apparatus includes an illumination system which applies illumination light for crystallization to a non-single-crystal semiconductor film, and a phase shifter which includes first and second regions disposed to form a straight boundary and transmitting the illumination light from the illumination system by a first phase retardation therebetween, and phase-modulates the illumination light to provide a light intensity distribution having an inverse peak pattern that light intensity falls in a zone of the non-single-crystal semiconductor film containing an axis corresponding to the boundary. The phase shifter further includes a small region which extends into at least one of the first and second regions from the boundary and transmits the illumination light by a second phase retardation with respect to the at least one of the first and second regions.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: March 17, 2009
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Patent number: 7504126
    Abstract: A plasma display panel is composed of a first substrate and a second substrate facing each other via a discharge space and sealed together. A protective layer on the first substrate is composed principally of magnesium oxide, includes a substance or structure that creates a first energy level in an area of a forbidden band, the area being in a vicinity of a conduction band, and includes a substance or structure that creates a second energy level in another area in the forbidden band, the other area being in a vicinity of a valence band. During driving the second energy level is occupied by electrons, and few electrons exist in the first energy level, or electrons can easily occupy the first energy level due to a minus charge state, and MgO insultaive resistance is not lowered. This maintains wall charge retention and reduces discharge irregularities and firing voltage Vf.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: March 17, 2009
    Assignee: Panasonic Corporation
    Inventors: Mikihiko Nishitani, Yukihiro Morita, Masatoshi Kitagawa, Masaharu Terauchi
  • Patent number: 7501763
    Abstract: Provided is a gas discharge display panel that exhibits a favorable display performance by maintaining a wall charge retaining power, controlling discharge delay within a range adequate for optimal image display, and reducing the discharge starting voltage at comparatively low cost. Also provided is a PDP that exhibits more reliability with enhanced display quality by further improving the secondary electron emission factor ? compared to conventional cases and lowering the discharge starting voltage to widen the driving margin. In addition, provided is a manufacturing method of a gas discharge display panel, by which the manufacturing cost lowers by reduction of the exhaustion time in the sealing exhaustion process, and by which the driving circuit cost is reduced. In the present invention, the protective layer contains, with respect to a MgO content of the protective layer, Si in a range of 20 mass ppm to 5000 mass ppm inclusive and H in a range of 300 mass ppm to 10000 mass ppm inclusive.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: March 10, 2009
    Assignee: Panasonic Corporation
    Inventors: Jun Hashimoto, Masatoshi Kitagawa, Mikihiko Nishitani, Masaharu Terauchi, Shinichi Yamamoto
  • Publication number: 20080315768
    Abstract: A PDP (101) with a reduced discharge inception voltage and discharge sustaining voltage for improving luminous efficiency has at least a pair of substrates (110 and 111) that are disposed in opposition to sandwich a discharge space therebetween. At least a portion of at least one of the substrates has two or more display electrode pairs (104) that include narrow bus electrodes (159 and 169), a dielectric layer (107) formed so as to cover the display electrode pairs (104), and a protective layer (108) formed so as to cover the dielectric layer (107). The dielectric layer (107) has a dense film structure with a dielectric breakdown voltage of 1.0×106 [V/cm] to 1.0×107 [V/cm].
    Type: Application
    Filed: August 11, 2005
    Publication date: December 25, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroyuki Yamakita, Masatoshi Kitagawa, Mikihiko Nishitani
  • Publication number: 20080278074
    Abstract: Provided is a gas discharge display panel that exhibits a favorable display performance by maintaining a wall charge retaining power, controlling discharge delay within a range adequate for optimal image display, and reducing the discharge starting voltage at comparatively low cost. Also provided is a PDP that exhibits more reliability with enhanced display quality by further improving the secondary electron emission factor ? compared to conventional cases and lowering the discharge starting voltage to widen the driving margin. Further provided is a manufacturing method of a gas discharge display panel, by which the manufacturing cost lowers by reduction of the exhaustion time in the sealing exhaustion process, and by which the driving circuit cost is reduced.
    Type: Application
    Filed: April 7, 2005
    Publication date: November 13, 2008
    Inventors: Shinichi Yamamoto, Mikihiko Nishitani, Masaharu Terauchi, Jun Hashimoto, Masatoshi Kitagawa
  • Patent number: 7432656
    Abstract: A plasma display panel in which a first substrate having a protective layer formed thereon opposes a second substrate across a discharge space, with the substrates being sealed around a perimeter thereof. At a surface of the protective layer, first and second materials of different electron emission properties are exposed to the discharge space, with at least one of the materials existing in a dispersed state. The first and second materials may be first and second crystals, and the second crystal may be dispersed throughout the first crystal.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 7, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukihiro Morita, Masatoshi Kitagawa, Kiichiro Oishi, Mikihiko Nishitani
  • Publication number: 20080211408
    Abstract: An object of the present invention is to provide a plasma display panel and a manufacturing method thereof that can prevent a dielectric layer and a protective layer from being deteriorated and give excellent image display performance, by performing a sealing process effectively. The object can be realized by a plasma display panel including a front panel 10 and a back panel 11 arranged in opposing to each other at a certain gap, the front panel and the back panel being sealed by a sealing layer 17 that is provided on entire peripheral portions of main surfaces of the front panel and the back panel, and the sealing layer is composed of at least one material selected from the group consisting of an organic resin material, an inorganic material, and a metal material (more specifically, a silica material as a main component and an epoxy resin material).
    Type: Application
    Filed: August 11, 2005
    Publication date: September 4, 2008
    Inventors: Hiroyuki Yamakita, Masatoshi Kitagawa, Mikihiko Nishitani, Noriyasu Echigo, Tomohiro Okumura, Hiroaki Ishio, Hikaru Nishitani
  • Patent number: 7413608
    Abstract: A crystallization apparatus includes an illumination system which applies illumination light for crystallization to a non-single-crystal semiconductor film, and a phase shifter which includes first and second regions disposed to form a straight boundary and transmitting the illumination light from the illumination system by a first phase retardation therebetween, and phase-modulates the illumination light to provide a light intensity distribution having an inverse peak pattern that light intensity falls in a zone of the non-single-crystal semiconductor film containing an axis corresponding to the boundary. The phase shifter further includes a small region which extends into at least one of the first and second regions from the boundary and transmits the illumination light by a second phase retardation with respect to the at least one of the first and second regions.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: August 19, 2008
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Publication number: 20080157672
    Abstract: Disclosed is a PDP and a manufacturing method therefor having improved display performance even if the PDP is of a fine-cell structure. A protective layer of the PDP is composed of an MgO film layer and an MgO particle layer that is made of MgO particles. The MgO particles are formed by burning an MgO precursor and satisfy that a/b?1, where a denotes a spectrum integral value in a wavelength region of a CL spectrum from 200 nm to 300 nm, exclusive of 300 nm, and b denotes a spectrum integral value in a wavelength region of the CL spectrum from 300 nm to 550 nm, exclusive of 550 nm. With provision of the MgO particle layer, the discharge characteristics of the protective layer improve (shorter discharge delay and less temperature dependence of the discharge delay). Consequently, the PDP is ensured to exhibit excellent display performance.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 3, 2008
    Inventors: Takuji Tsujita, Yusuke Fukui, Masaharu Terauchi, Mikihiko Nishitani, Michiko Okafuji, Shinichiro Ishino, Kaname Mizokami