Patents by Inventor Mikihiko Nishitani

Mikihiko Nishitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040145316
    Abstract: A plasma display panel is composed of a first substrate and a second substrate facing each other via a discharge space and sealed together. A protective layer on the first substrate is composed principally of magnesium oxide, includes a substance or structure that creates a first energy level in an area of a forbidden band, the area being in a vicinity of a conduction band, and includes a substance or structure that creates a second energy level in another area in the forbidden band, the other area being in a vicinity of a valence band. During driving the second energy level is occupied by electrons, and few electrons exist in the first energy level, or electrons can easily occupy the first energy level due to a minus charge state, and MgO insultaive resistance is not lowered. This maintains wall charge retention and reduces discharge irregularities and firing voltage Vf.
    Type: Application
    Filed: November 6, 2003
    Publication date: July 29, 2004
    Inventors: Mikihiko Nishitani, Yukihiro Morita, Masatoshi Kitagawa, Masaharu Terauchi
  • Publication number: 20040142544
    Abstract: A method of manufacturing a thin-film semiconductor device substrate includes a step of forming a non-single crystalline semiconductor thin film on a base layer, and an annealing step of irradiating the non-single crystalline semiconductor thin film with an energy beam to enhance crystallinity of a non-single crystalline semiconductor constituting the non-single crystalline semiconductor thin film. The annealing step includes simultaneously irradiating the non-single crystalline semiconductor thin film with a plurality of energy beams to form a plurality of unit regions each including at least one irradiated region irradiated with the energy beam and at least one non-irradiated region that is not irradiated with the energy beam.
    Type: Application
    Filed: January 13, 2004
    Publication date: July 22, 2004
    Inventors: Yoshinobu Kimura, Masakiyo Matsumura, Yoshitaka Yamamoto, Mikihiko Nishitani, Masato Hiramatsu, Masayuki Jyumonji, Fumiki Nakano
  • Publication number: 20040061149
    Abstract: The semiconductor device according to the present invention has a semiconductor layer having not smaller than two types of crystal grains different in size within a semiconductor circuit on a same substrate.
    Type: Application
    Filed: September 24, 2003
    Publication date: April 1, 2004
    Inventors: Masayuki Jyumonji, Masakiyo Matsumura, Yoshinobu Kimura, Mikihiko Nishitani, Masato Hiramatsu, Yukio Taniguchi, Fumiki Nakano, Hiroyuki Ogawa
  • Publication number: 20040058484
    Abstract: A crystallization apparatus includes an illumination system which applies illumination light for crystallization to a non-single-crystal semiconductor film, and a phase shifter which includes first and second regions disposed to form a straight boundary and transmitting the illumination light from the illumination system by a first phase retardation therebetween, and phase-modulates the illumination light to provide a light intensity distribution having an inverse peak pattern that light intensity falls in a zone of the non-single-crystal semiconductor film containing an axis corresponding to the boundary. The phase shifter further includes a small region which extends into at least one of the first and second regions from the boundary and transmits the illumination light by a second phase retardation with respect to the at least one of the first and second regions.
    Type: Application
    Filed: September 8, 2003
    Publication date: March 25, 2004
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Publication number: 20040036969
    Abstract: A crystallization apparatus includes an optical illumination system to illuminate a phase shift mask and which irradiates an amorphous semiconductor film with a light beam having an inverse peak type light intensity distribution including a minimum light intensity in a point corresponding to a phase shift portion of the phase shift mask to produce a crystallized semiconductor film. A wavefront dividing element is disposed on a light path between the optical illumination system and the phase shift mask. The wavefront dividing element wavefront-divides the light beam supplied from the optical illumination system into a plurality of light beams, and condenses the wavefront-divided light beams in the corresponding phase shift portion or in the vicinity of the portion.
    Type: Application
    Filed: June 26, 2003
    Publication date: February 26, 2004
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Publication number: 20040005744
    Abstract: A crystallization apparatus includes an illumination optical system to illuminate a phase shift mask and which irradiates an amorphous semiconductor film with a light beam having an intensity distribution of an inverse peak type having a smallest light intensity in a point corresponding to a phase shift portion of the phase shift mask to generate a crystallized semiconductor film. A convergence/divergence element is disposed on a light path between the illumination optical system and phase shift mask. The convergence/divergence element converts the light beam supplied from the illumination optical system into a light beam having an upward concave intensity distribution in which the light intensity is lowest in the phase shift portion and in which the light intensity increases as distant from the phase shift portion to irradiate the phase shift mask.
    Type: Application
    Filed: June 26, 2003
    Publication date: January 8, 2004
    Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
  • Publication number: 20030162332
    Abstract: There are disclosed a method and apparatus for forming a semiconductor film having an excellent crystallinity on a base layer made of an insulating material.
    Type: Application
    Filed: February 13, 2003
    Publication date: August 28, 2003
    Inventors: Masakiyo Matsumura, Mikihiko Nishitani, Yoshinobu Kimura, Masayuki Jyumonji, Yukio Taniguchi, Masato Hiramatsu, Fumiki Nakano
  • Publication number: 20030162373
    Abstract: By applying ion or optical energy or catalytic effects at the time of depositing a crystalline silicon thin film, improvements in crystallinity of the crystalline silicon thin film in proximities of an interface of a substrate or smoothing of its surface may be achieved. With this arrangement, it is possible to achieve improvements in crystallinity of the crystalline silicon film that is formed in a low temperature condition through CVD method and to prevent concaves and convexes from being formed on its surface or to prevent oxidation of grain fields, and it is accordingly possible to provide a thin film transistor, a semiconductor device such as a solar cell and methods for manufacturing these that exhibit superior characteristics and reliability.
    Type: Application
    Filed: March 6, 2003
    Publication date: August 28, 2003
    Applicant: Matsushita Elec. Ind. Co. Ltd.
    Inventors: Masashi Goto, Mikihiko Nishitani, Masaharu Terauchi
  • Publication number: 20030143784
    Abstract: A method of fabricating a thin film includes: forming, on a substrate, a thin film with film properties varying from region to region on the substrate, by selectively heating the substrate; and patterning the thin film in a predetermined pattern by etching the thin film to selectively remove only a portion of the thin film with specified film properties. The method reduces the fabrication process temperature and the number of fabrication steps, while inhibiting degradation in device performance.
    Type: Application
    Filed: October 3, 2002
    Publication date: July 31, 2003
    Inventors: Mikihiko Nishitani, Masashi Goto
  • Publication number: 20030132439
    Abstract: A method for producing a thin film semiconductor device is described. In the method, a thin film layer of non-single-crystalline semiconductor, which is deposited on a base layer of glass, is processed to an island-shaped thin film layer at the time prior to the layer irradiation step. The laser irradiation to the thin film layer of non-single-crystalline semiconductor is carried out after forming an insulation film layer and a gate electrode over the island-shaped thin film layer, by using the gate electrode as the irradiation mask, whereby the center area of the island-shaped thin film layer masked by the gate electrode is crystallized, and simultaneously, the both side areas thereof which is not masked by the gate electrode are annealed. Next, a source electrode and a drain electrode is formed in the annealed areas. The implantation of impurity ion may be carried out either before or after the laser irradiation.
    Type: Application
    Filed: November 14, 2002
    Publication date: July 17, 2003
    Applicant: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yoshinobu Kimura, Masakiyo Matsumura, Mikihiko Nishitani, Masato Hiramatsu, Masayuki Jyumonji, Yoshitaka Yamamoto, Hideo Koseki
  • Patent number: 6548380
    Abstract: By applying ion or optical energy or catalytic effects at the time of depositing a crystalline silicon thin film, improvements in crystallinity of the crystalline silicon thin film in proximities of an interface of a substrate or smoothing of its surface may be achieved. With this arrangement, it is possible to achieve improvements in crystallinity of the crystalline silicon film that is formed in a low temperature condition through CVD method and to prevent concaves and convexes from being formed on its surface or to prevent oxidation of grain fields, and it is accordingly possible to provide a thin film transistor, a semiconductor device such as a solar cell and methods for manufacturing these that exhibit superior characteristics and reliability.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: April 15, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masashi Goto, Mikihiko Nishitani, Masaharu Terauchi
  • Patent number: 6528397
    Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203 is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: March 4, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinao Taketomi, Keizaburo Kuramasu, Masumi Izuchi, Hiroshi Satani, Hiroshi Tsutsu, Hikaru Nishitani, Mikihiko Nishitani, Masashi Goto, Yoshiko MIno
  • Publication number: 20030022471
    Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203. is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.
    Type: Application
    Filed: August 15, 2002
    Publication date: January 30, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinao Taketomi, Keizaburo Kuramasu, Masumi Izuchi, Hiroshi Satani, Hiroshi Tsutsu, Hikaru Nishitani, Mikihiko Nishitani, Masashi Goto, Yoshiko Mino
  • Publication number: 20020179589
    Abstract: The present invention relates to an improvement in lamp-annealing devices for annealing a semiconductor film formed on a transparent substrate. In the present invention, a lamp-annealing device is provided with a means for selectively heating a semiconductor film, and a rise in temperature in the substrate during annealing is inhibited. Furthermore, feedback control of the annealing process is carried out based on the light reflected or the light transmitted by the annealed semiconductor film.
    Type: Application
    Filed: October 5, 2001
    Publication date: December 5, 2002
    Inventors: Yukihiro Morita, Mikihiko Nishitani, Munehiro Shibuya
  • Patent number: 6162296
    Abstract: The method and the apparatus of manufacturing the I-III-VI.sub.2 type chalcopyrite semiconductor thin films of the present invention control the film composition easily and improve the reproducibility of films by monitoring the composition of the films during forming the films. The apparatus comprise the substrate holder and heater which are in the vacuum chamber and Mo-coated glass substrate on which Cu(In,Ga)Se.sub.2 films are deposited. The change of the substrate temperature is monitored by the use of a heating element to heat the substrate by releasing a certain quantity of heat, a mechanism of measuring a temperature of the heated substrate. The change of power supplied is monitored by the use of a power source for the heating element to keep the substrate at a certain temperature and a mechanism of monitoring the change of the power supplied to the heating element. The changes in substrate temperature or power supplied can be correlated to the film composition.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: December 19, 2000
    Assignee: Mitsushita Electric Industrial Co., Ltd.
    Inventors: Naoki Kohara, Takayuki Negami, Mikihiko Nishitani, Takahiro Wada
  • Patent number: 6023020
    Abstract: A solar cell utilizing a chalcopyrite semiconductor and reducing the density of defects on the junction interface of pn junctions is provided. This solar cell includes a substrate, a back electrode formed on the substrate, a p-type chalcopyrite semiconductor thin film formed on the back electrode, an n-type semiconductor thin film formed so as to constitute a pn junction with the p-type chalcopyrite semiconductor thin film, and a transparent electrode formed on the n-type semiconductor thin film. A material having a higher resistivity than the p-type chalcopyrite semiconductor is formed between the p-type chalcopyrite semiconductor thin film and the n-type semiconductor thin film. A thin film made of this material may be formed by deposition from a solution. For example, CuInS.sub.2 is formed on the surface of a p-type chalcopyrite based semiconductor such as CuInSe.sub.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: February 8, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mikihiko Nishitani, Takayuki Negami, Naoki Kohara, Takahiro Wada, Yasuhiro Hashimoto
  • Patent number: 5918111
    Abstract: The method and the apparatus of manufacturing the I-III-VI.sub.2 type chalcopyrite semiconductor thin films of the present invention control the film composition easily and improve the reproducibility of films by monitoring the composition of the films during forming the films. The apparatus comprise the substrate holder and heater which are in the vacuum chamber and Mo-coated glass substrate on which Cu(In,Ga)Se.sub.2 films are deposited. The change of the substrate temperature is monitored by the use of a heating element to heat the substrate by releasing a certain quantity of heat, a mechanism of measuring a temperature of the heated substrate. The change of power supplied is monitored by the use of a power source for the heating element to keep the substrate at a certain temperature and a mechanism of monitoring the change of the power supplied to the heating element. The changes in substrate temperature or power supplied can be correlated to the film composition.
    Type: Grant
    Filed: March 11, 1996
    Date of Patent: June 29, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naoki Kohara, Takayuki Negami, Mikihiko Nishitani, Takahiro Wada
  • Patent number: 5858121
    Abstract: A thin film solar cell having high conversion efficiency is provided. The band gap of the thin film solar cell can be controlled while keeping the quality superior to conventional solar cells. The absorber layer for photovoltaic energy conversion is a Cu(In.sub.1-X Ga.sub.X)(Se.sub.1-Y S.sub.Y).sub.2 based solid solution where X and Y are in the range of the following Equation:0.317+0.176Y.gtoreq.X.gtoreq.0.117+0.176Y1>X+Y>0Y>0,The Cu(In.sub.1-X Ga.sub.X)(Se.sub.1-Y S.sub.Y).sub.2 based solid solution has a specific chalcopyrite type crystal structure and its lattice constant ratio of c-axis to a-axis is extremely close to two. It is most preferable that the band gap is 1.4 eV, X is 0.3, and Y is 0.4, since the conversion efficiency of a homojunction solar cell will then become a maximum.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: January 12, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takahiro Wada, Mikihiko Nishitani, Naoki Kohara
  • Patent number: 5728231
    Abstract: A precursor for manufacturing a semiconductor thin film in which an oxide thin film comprising at least one element as a dopant, selected from a group which consists of Groups IA, IIA, IIB, VA, and VB elements, and Groups IB and IIIA elements which are main components of the semiconductor thin film are deposited on a substrate, or a precursor for manufacturing a semiconductor thin film which is formed by depositing a thin film of oxide comprising the Groups IB and IIIA elements on the substrate wherein the content of at least one of the Groups IB and IIIA elements is varied in the direction of film thickness, and a method for manufacturing a semiconductor thin film comprising the step of heat treating the precursor for manufacturing the semiconductor thin film in an atmosphere containing a Group VIA element.
    Type: Grant
    Filed: May 15, 1996
    Date of Patent: March 17, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takayuki Negami, Masaharu Terauchi, Mikihiko Nishitani, Takahiro Wada
  • Patent number: 5725671
    Abstract: An apparatus for manufacturing an ABC.sub.2 chalcopyrite film (wherein A represents Cu or Ag, B represents In, Ga or Al, C represents S, Se or Te) includes a substrate holder, a substrate heater, a supply source for supplying elements A, B or C onto the substrate and for controlling the supply process, and a monitor for monitoring an electrical or optical property of the thin film layer deposited on the substrate. The electrical or optical property of the thin film layer abruptly changes at a first time point when the A/B ratio in the thin film layer changes from an element A-excessive state to the stoichiometric composition ratio of the ABC.sub.2. The electrical or optical property of the thin film layer demonstrates a stable value at a second time point when the A/B ratio becomes an element-B excessive state. Deposition is terminated at the second time point.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: March 10, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mikihiko Nishitani, Takayuki Negami, Takahiro Wada