Patents by Inventor Min Cheng

Min Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200354625
    Abstract: The instant application relates to nanogels or compositions that hold multivalent metal ions until some level of nanogel degradation has occurred, then slowly release the multivalent metal ions for gelation with carboxylate containing polymers. Compositions comprising such nanogels, together with polymers that can be crosslinked with multivalent metal ions, allow the deployment of such mixtures in various applications, and greatly increased gelation times.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Inventors: Huili GUAN, Cory BERKLAND, Ahmad MORADI-ARAGHI, Jenn-Tai LIANG, Terry M. CHRISTIAN, Riley B. NEEDHAM, Min CHENG, Faye Lynn SCULLY, James H. HEDGES
  • Publication number: 20200350317
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 10817015
    Abstract: A display device includes at least one speaker, a signal transceiver and a processor. The at least one speaker outputs a sound according to a volume parameter. The signal transceiver receives incoming call information from a communication device. The processor is electrically coupled to the at least one speaker and the signal transceiver. The processor detects signal strength of the communication device and adjusts the volume parameter according to the incoming call information and the signal strength, in order to increase or decrease a volume of the sound.
    Type: Grant
    Filed: March 17, 2019
    Date of Patent: October 27, 2020
    Assignee: AMTRAN TECHNOLOGY CO., LTD.
    Inventors: Chiung-Wen Tseng, Min-Cheng Wu, Yi-Xuan Huang
  • Patent number: 10815320
    Abstract: Polar silane linkers are provided that attach to resins to form silane-functionalized resins. The functionalized resins can be bound to hydroxyl groups on the surface of silica particles to improve the dispersibility of the silica particles in rubber mixtures. Further disclosed are synthetic routes to provide the silane-functionalized resins, as well as various uses and end products that benefit from the unexpected properties of the silane-functionalized resins. Silane-functionalized resins impart remarkable properties on various rubber compositions, such as tires, belts, hoses, brakes, and the like. Automobile tires incorporating the silane-functionalized resins are shown to possess excellent results in balancing the properties of rolling resistance, tire wear, and wet braking performance.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 27, 2020
    Assignee: Eastman Chemical Company
    Inventors: Emily Baird Anderson, John Dayton Baker, Jr., Terri Roxanne Carvagno, Judicael Jacques Chapelet, Wei Min Cheng, Liu Deng, Jacobus Gillis De Hullu, Sebastian Finger, Hubert Hirschlag, Christopher Lee Lester, Wentao Li, Mutombo Joseph Muvundamina, Mark Stanley Pavlin, Fabian Peters, Carla Recker, Christopher Thomas Scilla
  • Patent number: 10811300
    Abstract: A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Min-Cheng Wu
  • Patent number: 10804365
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 13, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Publication number: 20200319137
    Abstract: An electrochemical cell for sensing gas has added mechanical support for the working electrode to prevent flexure of the working electrode due to pressure differentials. The added mechanical support includes: 1) affixing a larger area of the working electrode to the body of the cell; 2) a gas vent to a cavity of the body to equalize pressures; 3) a rigid electrolyte layer abutting a back surface of the working electrode; 4) infusing an adhesive deep into sides of the porous working electrode to enhance rigidity; 5) supporting opposing surfaces of the working electrode with the rigid package body; and 6) other techniques to make the working electrode more rigid. A bias circuit is also described that uses a controllable current source, an integrator of the varying current, and a feedback circuit for supplying a voltage to the counter electrode and a bias voltage to the reference electrode.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 8, 2020
    Inventors: Jim Chih-Min Cheng, Eric Paul Lee, Jerome Chandra Bhat
  • Publication number: 20200301292
    Abstract: A system includes a frame, a projection lens, a wafer table, and a cleaner. The frame has an opening vertically extending through the frame. The projection lens is disposed on the frame. The wafer table is below the frame, in which the wafer table is movable along a horizontal direction. The cleaner is over the frame, in which the cleaner comprises a sticky structure movable along a vertical direction and through the opening of the frame.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Cheng WU, Chi-Hung LIAO
  • Patent number: 10775706
    Abstract: A method of lithography includes obtaining a profile of a single field of a substrate that having a photoresist layer thereon, in which the profile includes a first feature and a second feature having different heights. A depth of focus distribution map is generated according to the profile. A project lens is tuned based on the generated depth of focus distribution map, such that the project lens provides a first focus length in a first project pixel of the project lens and a second focus length in a second project pixel of the project lens, wherein the first focus length and the second focus lengths. The single field of the substrate is exposed by using the tuned project lens.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Min-Cheng Wu
  • Patent number: 10775700
    Abstract: A method is provided. The method includes steps as follows. EUV light is generated. A collector is used to gather the EUV light onto a first optical reflector. The first optical reflector is used to reflect the EUV light to a reticle, so as to impart the EUV light with a pattern. A second optical reflector is used to reflect the EUV light with the pattern onto a wafer. The first optical reflector is rotated.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hung Liao, Min-Cheng Wu
  • Publication number: 20200285277
    Abstract: A motor assembly is provided. The motor assembly includes a motor, a driving force transmission module, and a driving force output component. The motor includes a rotating shaft, the rotating shaft is configured to rotate along a first axis. The driving force transmission module includes a first transmission portion and a second transmission portion connected with each other. The first transmission portion is connected with the rotating shaft of the motor, and the second transmission portion is bent relative to the first transmission portion and extends to one side of the motor. The driving force output component is connected with an end of the second transmission portion away from the first transmission portion, and configured to rotate along a second axis, which is parallel to the first axis.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 10, 2020
    Inventors: Chui-Hung CHEN, Cheng-Han CHUNG, Ching-Yuan YANG, Chia-Min CHENG
  • Publication number: 20200288002
    Abstract: A functional assembly and an electronic device including the functional assembly are provided. The functional assembly includes a functional module, a motor, and a linking mechanism. The functional module has a first shaft. The motor has a second shaft and is configured to drive the second shaft to rotate. The linking mechanism is connected with the first shaft and the second shaft such that the first shaft and the second shaft are linking-up with each other. As a result, the thickness of the electronic device near the frame is not limited by the size of the motor, which further reduces the thickness of the electronic device.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 10, 2020
    Inventors: Cheng-Han CHUNG, Chui-Hung CHEN, Chia-Min CHENG, Ching-Yuan YANG
  • Publication number: 20200277471
    Abstract: Polar silane linkers are provided that attach to resins to form silane-functionalized resins. The functionalized resins can be bound to hydroxyl groups on the surface of silica particles to improve the dispersibility of the silica particles in rubber mixtures. Further disclosed are synthetic routes to provide the silane-functionalized resins, as well as various uses and end products that benefit from the unexpected properties of the silane-functionalized resins. Silane-functionalized resins impart remarkable properties on various rubber compositions, such as tires, belts, hoses, brakes, and the like. Automobile tires incorporating the silane-functionalized resins are shown to possess excellent results in balancing the properties of rolling resistance, tire wear, and wet braking performance.
    Type: Application
    Filed: April 9, 2018
    Publication date: September 3, 2020
    Applicant: Continental Reifen Deutschland GmbH
    Inventors: Fabian Peters, Emily Baird Anderson, John Dayton Baker, Jr., Terri Roxanne Carvagno, Judicael Jacques Chapelet, Wei Min Cheng, Liu Deng, Jacobus Gillis de Hullu, Sebastian Finger, Hubert Hirschlag, Christopher Lee Lester, Wentao Li, Mutombo Joseph Muvundamina, Mark Stanley Pavlin, Carla Recker, Christopher Thomas Scilla
  • Publication number: 20200273741
    Abstract: A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Chi-Hung Liao, Min-Cheng Wu
  • Patent number: 10752826
    Abstract: The instant application relates to nanogels or compositions that hold multivalent metal ions until some level of nanogel degradation has occurred, then slowly release the multivalent metal ions for gelation with carboxylate containing polymers. Compositions comprising such nanogels, together with polymers that can be crosslinked with multivalent metal ions, allow the deployment of such mixtures in various applications, and greatly increased gelation times.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: August 25, 2020
    Assignees: ConocoPhillips Company, University of Kansas
    Inventors: Huili Guan, Cory Berkland, Ahmad Moradi-Araghi, Jenn-Tai Liang, Terry M. Christian, Riley B. Needham, Min Cheng, Faye Lynn Scully, James H. Hedges
  • Patent number: 10756090
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 25, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Publication number: 20200266199
    Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Publication number: 20200258889
    Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Yi-Wei Chen, Pin-Hong Chen, Tsun-Min Cheng, Chun-Chieh Chiu
  • Publication number: 20200258201
    Abstract: The present disclosure relates to systems and methods for image sharpening. The systems and methods may obtain a target image to be processed, the target image including one or more target pixels to be processed. For each of the one or more target pixels, the systems and methods may select one or more previous pixels and one or more subsequent pixels along a predetermined direction in the target image; determine a first gray value based on the one or more previous pixels and a second gray value based on the one or more subsequent pixels; select a target gray value from the first gray value and the second gray value based on an initial gray value of the target pixel; and determine an adjusted gray value of the target pixel based on the initial gray value and the target gray value.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Applicant: ZHEJIANG DAHUA TECHNOLOGY CO., LTD.
    Inventors: Min CHENG, Keqiang YU
  • Patent number: 10732141
    Abstract: An electrochemical cell for sensing gas has added mechanical support for the working electrode to prevent flexure of the working electrode due to pressure differentials. The added mechanical support includes: 1) affixing a larger area of the working electrode to the body of the cell; 2) a gas vent to a cavity of the body to equalize pressures; 3) a rigid electrolyte layer abutting a back surface of the working electrode; 4) infusing an adhesive deep into sides of the porous working electrode to enhance rigidity; 5) supporting opposing surfaces of the working electrode with the rigid package body; and 6) other techniques to make the working electrode more rigid. A bias circuit is also described that uses a controllable current source, an integrator of the varying current, and a feedback circuit for supplying a voltage to the counter electrode and a bias voltage to the reference electrode.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: August 4, 2020
    Assignee: InSyte Systems
    Inventors: Jim Chih-Min Cheng, Eric Paul Lee, Jerome Chandra Bhat