Patents by Inventor Min Chu

Min Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152947
    Abstract: A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: October 19, 2021
    Assignee: Renesas Electronics America Inc.
    Inventor: Min Chu
  • Patent number: 11152341
    Abstract: In some examples, an integrated circuit includes a plurality of power modules formed on a substrate, including a first power module located between second and third power modules. The first power module is configured to conduct a load current, and includes a power transistor and first and second sense transistors. The first sense transistor is disposed at a first position between the second power module and a central axis of the first power module, and the second sense transistor is disposed at a second position between the third power module and the central axis. The first sense transistor is configured to conduct a first sense current; and the second sense transistor is configured to conduct a second sense current. The first and second sense transistors are configured to direct the first and second sense currents toward a measurement circuit that is configured to determine a derived sense current indicative of the load current.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: October 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kuntal Joardar, Min Chu, Vijay Krishnamurthy, Tikno Harjono
  • Patent number: 11123393
    Abstract: The present disclosure provides mixtures of prenylated flavonoids, stilbenes, or both with flavans or curcuminoids or both capable of modulating joint inflammation, joint pain, joint stiffness, cartilage degradation, or improving mobility, range of motion, flexibility, joint physical function, or any combination thereof. Such a mixture of prenylated flavonoids, stilbenes, or both with flavans or curcuminoids or both can optionally be used in combination with other joint management agents, such as non-steroidal anti-inflammatory agents/analgesics, COX/LOX inhibiting agents, glucosamine compounds, neuropathic pain relief agents, or the like.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: September 21, 2021
    Assignee: Unigen, Inc.
    Inventors: Lidia Alfaro Brownell, Min Chu, Mei-Feng Hong, Eu-Jin Hyun, Qi Jia, Ping Jiao, Hyun-Jin Kim, Mi-Ran Kim, Tae-Woo Kim, Bo-Su Lee, Young-Chul Lee, Breanna Moore, Jeong-Bum Nam, Mi-Sun Oh, Mi-Hye Park, Mesfin Yimam, Qian Zhang
  • Patent number: 11121949
    Abstract: Example task assignment methods disclosed herein for video analytics processing in a cloud computing environment include determining a graph, such as a directed acyclic graph, including nodes and edges to represent a plurality of video sources, a cloud computing platform, and a plurality of intermediate network devices in the cloud computing environment. Disclosed example task assignment methods also include specifying task orderings for respective sequences of video analytics processing tasks to be executed in the cloud computing environment on respective video source data generated by respective ones of the video sources.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Hong-Min Chu, Shao-Wen Yang, Yen-Kuang Chen
  • Patent number: 11079723
    Abstract: A time-to-digital converter obtains a Start signal to indicate the start of an event, and a Stop signal whose assertion indicates the stop of the event. The Stop signal can be asserted multiple times due to false indications of the event stop. The TDC continuously monitors the Stop signal to generate a separate digital value for the duration from the event's starting time to each assertion of the Stop signal. The digital values can be analyzed to select the true duration of the event. Other features and embodiments are also provided.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: August 3, 2021
    Assignee: Integrated Device Technology, Inc.
    Inventors: Min Chu, Jagdeep Singh Bal
  • Publication number: 20210201167
    Abstract: The present application discloses a method of knowledge sharing between dialogue systems, including: receiving, by a first dialogue system, a knowledge sharing request sent by an external dialogue system, wherein the knowledge sharing request comprises at least feature information of a knowledge point to be shared by the external dialogue system; parsing the knowledge sharing request to determine the feature information of the knowledge point to be shared; and adding the feature information of the knowledge point to be shared to a knowledge base of the first dialogue system to form a shared knowledge base. The embodiment of the present application realizes the sharing of knowledge among different dialogue systems by sharing knowledge points among dialogue systems, and meets the cross-domain dialogue needs of users for dialogue robots to the greatest extent while minimizing costs.
    Type: Application
    Filed: May 21, 2019
    Publication date: July 1, 2021
    Applicant: Al Speech Co., Ltd.
    Inventors: Fujiang GE, Min CHU, Taotao GUO, Zhongyuan DAI
  • Patent number: 10950557
    Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: March 16, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin, Chien-Wen Huang
  • Publication number: 20210025925
    Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents is less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.
    Type: Application
    Filed: October 13, 2020
    Publication date: January 28, 2021
    Inventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
  • Publication number: 20210008101
    Abstract: The present invention relates to methods and compositions for preventing, reducing or eradicating toxicity caused by acetaminophen (APAP). Specifically, the toxicity is nephrotoxicity and/or hepatotoxicity.
    Type: Application
    Filed: February 14, 2019
    Publication date: January 14, 2021
    Applicant: SINEW PHARMA INC.
    Inventors: Oliver Yoa-Pu HU, Tung-Yuan SHIH, Cheng-Huei HSIONG, Hsin-Tien HO, Kai-Min CHU
  • Publication number: 20210005587
    Abstract: In some examples, an integrated circuit includes a plurality of power modules formed on a substrate, including a first power module located between second and third power modules. The first power module is configured to conduct a load current, and includes a power transistor and first and second sense transistors. The first sense transistor is disposed at a first position between the second power module and a central axis of the first power module, and the second sense transistor is disposed at a second position between the third power module and the central axis. The first sense transistor is configured to conduct a first sense current; and the second sense transistor is configured to conduct a second sense current. The first and second sense transistors are configured to direct the first and second sense currents toward a measurement circuit that is configured to determine a derived sense current indicative of the load current.
    Type: Application
    Filed: July 2, 2019
    Publication date: January 7, 2021
    Inventors: Kuntal JOARDAR, Min CHU, Vijay KRISHNAMURTHY, Tikno HARJONO
  • Publication number: 20200395000
    Abstract: Disclosed is a human-computer dialogue method including determining a set number of jump topics about a target topic, and generating a topic jump map converging to the target topic based on the correlation intensions among the set number of jump topics; after an initial response to a user's dialogue request, selecting from the topic jump map a jump topic to which the user's dialogue request relates as an initial topic for a first round of recommendation; after completing a human-machine dialogue of the initial topic, determining a jump topic to jump according to the jump probability of jumping out of the initial topic to the k jump topics at the downstream level for a next round of recommendation; and gradually guiding from the initial topic to the target topic by step-by-step recommendation. A more fluent and efficient human-machine dialogue based on a clear communication goal can be realized.
    Type: Application
    Filed: January 22, 2019
    Publication date: December 17, 2020
    Applicant: AI SPEECH CO., LTD
    Inventors: Min CHU, Taotao GUO, Zhongyuan DAI, Chao YANG
  • Patent number: 10837986
    Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
  • Publication number: 20200322238
    Abstract: Example task assignment methods disclosed herein for video analytics processing in a cloud computing environment include determining a graph, such as a directed acyclic graph, including nodes and edges to represent a plurality of video sources, a cloud computing platform, and a plurality of intermediate network devices in the cloud computing environment. Disclosed example task assignment methods also include specifying task orderings for respective sequences of video analytics processing tasks to be executed in the cloud computing environment on respective video source data generated by respective ones of the video sources.
    Type: Application
    Filed: January 7, 2020
    Publication date: October 8, 2020
    Inventors: Hong-Min Chu, Shao-Wen Yang, Yen-Kuang Chen
  • Publication number: 20200266823
    Abstract: A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 20, 2020
    Inventor: Min CHU
  • Publication number: 20200222304
    Abstract: The present disclosure provides a mixture of sugar apple and rosemary extracts, optionally in combination with prickly ash extract, for use as skin care compositions.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Applicant: Unigen, Inc.
    Inventors: Lidia Alfaro Brownell, Min Chu, Brandon Corneliusen, Mei-Feng Hong, Ji-Hye Hwang, Eu-Jin Hyun, Qi Jia, Ping Jiao, Mi-Ran Kim, Bo-Su Lee, Young-Chul Lee, Jeong-Bum Nam, Mi-Sun Oh, Mesfin Yimam
  • Patent number: 10679938
    Abstract: An electronic device comprises a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a first gate, a first terminal, and a second terminal; a first sense transistor integrated in the first semiconductor die, the first sense transistor comprising a second gate and third and fourth terminals, the second gate coupled to the first gate and the fourth terminal coupled to the second terminal; a first resistor integrated in the first semiconductor die, the first resistor has a first temperature coefficient; a second sense transistor integrated in the first semiconductor die, the second sense transistor comprising a third gate and seventh and eighth terminals, the third gate coupled to the first gate and the eighth terminal coupled to the second terminal; and a second resistor integrated in the first semiconductor die, the second resistor has a second temperature coefficient.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 9, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kuntal Joardar, Min Chu, Vijay Krishnamurthy, Tikno Harjono, Ankur Chauhan, Vinayak Hegde, Manish Srivastava
  • Publication number: 20200174045
    Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Inventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
  • Publication number: 20200176395
    Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.
    Type: Application
    Filed: February 4, 2020
    Publication date: June 4, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin, Chien-Wen Huang
  • Patent number: 10670638
    Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: June 2, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Vijay Krishnamurthy, Abidur Rahman, Min Chu, Sualp Aras
  • Patent number: 10622811
    Abstract: Disclosed in a stand-alone micro-grid autonomous control system including: at least one battery system directly changing a reference frequency thereof according to a charge amount, and providing power having the changed reference frequency; at least one power generator measuring the reference frequency from the power provided form the at least one battery system, and starting generating power or stopping generating power based on the measured reference frequency; and at least one load measuring the reference frequency from the power provided from the battery system, and performing a synchronization operation or a synchronization releasing operation based on the measured reference frequency.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: April 14, 2020
    Assignee: Korea Electric Power Corporation
    Inventors: Won-Wook Jung, Cheol-Min Chu, Jung-Sung Park, Sang-Yun Yun, Seong-Chul Kwon, Jeong-Hun Kim