Patents by Inventor Min Chu

Min Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180248374
    Abstract: Disclosed in a stand-alone micro-grid autonomous control system including: at least one battery system directly changing a reference frequency thereof according to a charge amount, and providing power having the changed reference frequency; at least one power generator measuring the reference frequency from the power provided form the at least one battery system, and starting generating power or stopping generating power based on the measured reference frequency; and at least one load measuring the reference frequency from the power provided from the battery system, and performing a synchronization operation or a synchronization releasing operation based on the measured reference frequency.
    Type: Application
    Filed: July 14, 2016
    Publication date: August 30, 2018
    Applicant: Korea Electric Power Corporation
    Inventors: Won-Wook JUNG, Cheol-Min CHU, Jung-Sung PARK, Sang-Yun YUN, Seong-Chul KWON, Jeong-Hun KIM
  • Publication number: 20180189667
    Abstract: A weighting value is determined for each of a plurality of decision trees in a random forest model hosted on a particular device, where the weighting is based on entropy of the respective decision tree. A new decision tree is received at the particular device and a weighting value is determined for the new decision tree based on entropy of the new decision tree. Based on the determined weighting value, it is determined whether to add the new the decision tree to the random forest model. A classification for data generated at the particular device is predicted using the random forest model.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventors: Yu-Lin Tsou, Shao-Wen Yang, Hong-Min Chu
  • Publication number: 20180152361
    Abstract: Example task assignment methods disclosed herein for video analytics processing in a cloud computing environment include determining a graph, such as a directed acyclic graph, including nodes and edges to represent a plurality of video sources, a cloud computing platform, and a plurality of intermediate network devices in the cloud computing environment. Disclosed example task assignment methods also include specifying task orderings for respective sequences of video analytics processing tasks to be executed in the cloud computing environment on respective video source data generated by respective ones of the video sources.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Inventors: Hong-Min Chu, Shao-Wen Yang, Yen-Kuang Chen
  • Publication number: 20180096261
    Abstract: An anomaly detection model generator accesses sensor data generated by a plurality of sensors, determines a plurality of feature vectors from the sensor data, and executes a plurality of unsupervised anomaly detection machine learning algorithms in an ensemble using the plurality of feature vectors to generate a set of predictions. Respective entropy-based weightings are determined for each of the plurality of unsupervised anomaly detection machine learning algorithms from the set of predictions. A set of pseudo labels is generated based on the predictions and weightings, and a supervised machine learning algorithm uses the set of pseudo labels as training data to generate an anomaly detection model corresponding to the plurality of sensors.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Hong-Min Chu, Yu-Lin Tsou, Shao-Wen Yang
  • Publication number: 20180090497
    Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Amey Mahadev Walke, Chi-Hsun Hsieh, Che-Min Chu, Yu-Hsuan Kuo
  • Publication number: 20180055899
    Abstract: The present disclosure provides mixtures of prenylated flavonoids, stilbenes, or both with flavans or curcuminoids or both capable of useful for promoting, managing or improving bone health, cartilage health or both, or for preventing or treating a bone disorder, cartilage disorder or both. Such a mixture of prenylated flavonoids, stilbenes, or both with flavans or curcuminoids or both can optionally be used in combination with other bone and cartilage management agents, such as calcium, magnesium, zinc, boron, vitamin D, vitamin K, glucosamine and/or chondroitin compounds, non-steroidal anti-inflammatory agents/analgesics, COX/LOX inhibiting agents, neuropathic pain relief agents, or the like.
    Type: Application
    Filed: July 30, 2017
    Publication date: March 1, 2018
    Applicants: Unigen, Inc., Unigen, Inc.
    Inventors: Lidia Alfaro Brownell, Min Chu, Mei-Feng Hong, Eu-Jin Hyun, Qi Jia, Ping Jiao, Hyun-Jin Kim, Mi-Ran Kim, Tae-Woo Kim, Young-Chul Lee, Jeong-Bum Nam, Mesfin Yimam
  • Patent number: 9859901
    Abstract: An apparatus includes a phase locked loop circuit having a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator. The apparatus includes at least one delay element disposed so as to enable contributing at least one of the following: i) delay to a signal provided to the first input of the phase comparator; ii) delay to a signal provided to the second input of the phase comparator. A delay contributed by the at least one delay element varies in accordance with an associated delay control value. The phase locked loop circuit and the at least one delay element reside on a same semiconductor substrate.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 2, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Min Chu, John C. Hsu, Ron D. Wade
  • Patent number: 9837416
    Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Amey Mahadev Walke, Chi-Hsun Hsieh, Che-Min Chu, Yu-Hsuan Kuo
  • Patent number: 9825010
    Abstract: A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: November 21, 2017
    Assignee: Powertech Technology Inc.
    Inventors: Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin, Chien-Wen Huang
  • Publication number: 20170287874
    Abstract: A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.
    Type: Application
    Filed: March 10, 2017
    Publication date: October 5, 2017
    Applicant: Powertech Technology Inc.
    Inventors: Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin, Chien-Wen Huang
  • Publication number: 20170287870
    Abstract: A stacked chip package structure includes a first chip, stud bumps, a second chip, pillar bumps, an encapsulant and conductive vias. The first stud bumps are respectively disposed on a plurality of first pads of the first chip, wherein each first stud bump includes a rough surface, and the rough surface of each first stud bump is rougher than a top surface of each first pad. The second chip is disposed on the first chip and exposes the first pads. The pillar bumps are respectively disposed on a plurality of second pads of the second chips. The encapsulant encapsulates the first chip and the second chip and exposes a top surface of each second stud bump. The first conductive vias penetrate the encapsulant and connect the first stud bumps. Each first conductive via covers the rough surface of each first stud bump.
    Type: Application
    Filed: March 10, 2017
    Publication date: October 5, 2017
    Applicant: Powertech Technology Inc.
    Inventors: Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin, Chien-Wen Huang
  • Patent number: 9717770
    Abstract: The present disclosure provides mixtures of prenylated flavonoids, stilbenes, or both with flavans or curcuminoids or both capable of useful for promoting, managing or improving bone health, cartilage health or both, or for preventing or treating a bone disorder, cartilage disorder or both. Such a mixture of prenylated flavonoids, stilbenes, or both with flavans or curcuminoids or both can optionally be used in combination with other bone and cartilage management agents, such as calcium, magnesium, zinc, boron, vitamin D, vitamin K, glucosamine and/or chondroitin compounds, non-steroidal anti-inflammatory agents/analgesics, COX/LOX inhibiting agents, neuropathic pain relief agents, or the like.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: August 1, 2017
    Assignee: Unigen, Inc.
    Inventors: Lidia Alfaro Brownell, Min Chu, Mei-Feng Hong, Eu-Jin Hyun, Qi Jia, Ping Jiao, Hyun-Jin Kim, Mi-Ran Kim, Tae-Woo Kim, Young-Chul Lee, Jeong-Bum Nam, Mesfin Yimam
  • Publication number: 20170206897
    Abstract: Analyzing textual data is disclosed, including by: receiving textual data; determining that the textual data is a candidate for analogy analysis based at least in part on at least a portion of the textual data matching an analogical question template; extracting a source substantive from the textual data; using the source substantive to determine a target substantive from a word vector model that is trained on a set of training data; and generating an answer including the target substantive based at least in part on an analogical answer template corresponding to the analogical question template.
    Type: Application
    Filed: January 12, 2017
    Publication date: July 20, 2017
    Inventors: Huixing Jiang, Jian Sun, Min Chu
  • Patent number: 9654121
    Abstract: An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as to generate the feedback clock signal, includes a calibration circuit. The calibration circuit is coupled to receive the reference clock signal and the fast clock signal and to provide a frequency band selection signal to the variable frequency oscillator. The calibration circuit includes a counting circuit for counting a number of cycles of the fast clock signal over a period of time defined by a number of cycles (M) of the reference clock signal.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 16, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Min Chu
  • Publication number: 20170110125
    Abstract: A method for initiating an operation using voice is provided. The method includes extracting one or more voice features based on first audio data detected in a use stage; determining a similarity between the first audio data and a preset first voice model according to the one or more voice features, wherein the first voice model is associated with second audio data of a user, and the second audio data is associated with one or more preselected voice contents; and executing an operation corresponding to the first voice model based on the similarity.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 20, 2017
    Inventors: Minqiang XU, Zhijie YAN, Jie GAO, Min CHU
  • Patent number: 9594389
    Abstract: Provided are a device and a method for automatically coordinating a protection device of a smart power distribution management system, wherein a protection coordination correction value of the protection device is calculated via topology analysis and system analysis of a distribution system so as to apply the result to a smart power distribution management system. The device for automatically coordinating a protection device as provided comprises: generating the topology information by obtaining the status information of the distribution system; setting machines, which transmit and received data when an event occurs, to communicate for each of a plurality of protection devices based on the topology information; calculating a system power flow including the power flow direction based on the topology information; and calculating a fault current which is generated upon the failure of the distribution system based on the topology information, thereby generating a protection coordination correction value.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 14, 2017
    Assignee: KOREA ELECTRIC POWER CORPORATION
    Inventors: Cheol-Min Chu, Sang-Yun Yun, Seong-Chul Kwon, Il-Keun Song
  • Patent number: 9590426
    Abstract: Disclosed herein is a system and method for managing a power distribution system in which has an improved system protection and fault section determination structure in consideration of distributed power supplies, has an improved server and communication structure for one-to-one synchronization measurement, and conducts real time system management and control. The system for managing the power distribution system uses field measurement data and an event signal to detect a protection coordination correction value of a protective device for protection of the system and a fault section of the power distribution system, performs real time system analysis using the field measurement data, and transmits control information including at least one of the protection coordination correction value, the fault section and the system analysis information to a DCP server.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: March 7, 2017
    Assignee: KOREA ELECTRIC POWER CORPORATION
    Inventors: Sang-Yun Yun, Cheol-Min Chu, Seong-Chul Kwon, Il-Keun Song
  • Patent number: 9590637
    Abstract: A frequency divider includes a multiplexer having a first input terminal coupled to receive a first value M and a second input terminal for receiving a second value that is M+LSB, the multiplexer is configured to alternately output the first value M and the second value. The frequency divider includes a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles. A divide-by-two counter having an input coupled to the output of the multi-modulus divider, is operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency of N, where N is equal to 2M+LSB. Duty cycle correction logic is coupled to the output of the divide-by-two counter and is configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when N is odd.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: March 7, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Pak-Kim Lau, Min Chu
  • Publication number: 20170033106
    Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: AMEY MAHADEV WALKE, CHI-HSUN HSIEH, CHE-MIN CHU, YU-HSUAN KUO
  • Cup
    Patent number: D775896
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 10, 2017
    Assignee: GREENFACE PACKAGING LTD.
    Inventor: Che-Min Chu