Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

Abstract: The present disclosure provides methods and systems for detecting multiple different nucleotides in a sample. In particular, the disclosure provides for detection of multiple different nucleotides in a sample utilizing fewer detection moieties than the number of nucleotides being detected and/or fewer imaging events than the number of nucleotides being detected.

Abstract: A method for training a machine learning model is described, comprising receiving, for each perturbation of a plurality of perturbations of model parameters of a starting version of the machine learning model, a change of loss of the machine learning model caused by the perturbation for a set of training data determined by feeding the set of training data to one or more perturbed versions of the machine learning model, estimating a gradient of the loss of the machine learning model with respect to the model parameters from the determined changes of loss and updating the starting version of the machine learning model to an updated version of the machine learning model by changing the model parameters in a direction for which the estimated gradient indicates a reduction of loss.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: A multifunctional single-interface electronic expansion device, comprising an external electronic expansion device and a power transmitting cable. The external electronic expansion device comprises a device body, an electrical connecting module, a data signal processing module, a power transmitting module, and a first assembling member. The device body comprises a first wall surface and a second wall surface. The electrical connecting module is disposed at the device body and is exposed from the first wall surface to be electrically connected with or detached from an interface of a first electronic device. The data signal processing module is electrically connected with the electrical connecting module. The power transmitting module is electrically connected with the electrical connecting module. The power transmitting module comprises a power transmitting interface exposed from the second wall surface.

Abstract: A semiconductor structure includes a substrate, a conductive via and a first insulation layer. The conductive via is through the substrate. The first insulation layer is between the substrate and the conductive via. A first surface of the first insulation layer facing the substrate and a second surface of the first insulation layer facing the conductive via are extended along different directions.

Abstract: The present application relates to a top plate jacking device and jacking construction method configured for V-shaped columns, the top plate jacking device comprising a temporary support pile comprises a plurality of pile holes arranged on a construction surface, a bottom end of the pile hole is cast-in-place with a bearing platform, a temporary support column is inserted on the bearing platform, a plurality of pillars are fixed at a top of the temporary support column, wherein comprises a plurality of vertically connected column segments, two adjacent column segments detachably connected vertically through a connecting component; a support block is provided at a top of the plurality of pillars, the top of the support block abuts against a lower surface of the top plate; a hydraulic jack is configured to jack the top plate and is provided with a plurality of intervals at the top of the temporary support column.

Abstract: A magnetic component includes a core, a winding, a lead frame and a conductive material. The winding is disposed in the core. A winding end of the winding extends to an outer periphery of the core. The lead frame is disposed on the outer periphery of the core. At least one hole is formed on the lead frame and corresponds to the winding end. The conductive material is disposed in the at least one hole. The conductive material is in contact with the winding end.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: Methods and devices of having an enclosure structure formed in a multi-layer interconnect and a through-silicon-via (TSV) extending through the enclosure structure. In some implementations, a protection layer is formed between the enclosure structure and the TSV.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: A light-folding element includes an object-side surface, an image-side surface, a reflection surface and a connection surface. The reflection surface is configured to reflect imaging light passing through the object-side surface to the image-side surface. The connection surface is connected to the object-side, image-side and reflection surfaces. The light-folding element has a recessed structure located at the connection surface. The recessed structure is recessed from the connection surface an includes a top end portion, a bottom end portion and a tapered portion located between the top end and bottom end portions. The top end portion is located at an edge of the connection surface. The tapered portion has two tapered edges located on the connection surface. The tapered edges are connected to the top end and bottom end portions. A width of the tapered portion decreases in a direction from the top end portion towards the bottom end portion.

Abstract: Lithium difluorophosphate, a preparation method therefor, and an application thereof. Lithium hexafluorophosphate and silicon tetrachloride are utilized to generate lithium difluorotetrachloro phosphate, then lithium difluorotetrachloro phosphate reacts with lithium carbonate to obtain a mixture of lithium difluorophosphate and lithium chloride, and then the mixture is purified to obtain high-purity lithium difluorophosphate. The method has simple steps, low cost, short reaction time, and a high conversion rate.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

Abstract: A 3D AND flash memory device includes a gate stack structure, a channel pillar, a first and a second conductive pillars, a charge storage structure, and a protective cap. The gate stack structure is disposed on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar penetrates through the gate stack structure. The first and the second conductive pillars are disposed in the channel pillar and penetrate through the gate stack structure, and the first and the second conductive pillars are separated from each other and each connected to the channel pillar. The charge storage structure is disposed between the gate layers and a sidewall of the channel pillar. The protective cap covers at least a top surface of the channel pillar and isolates the first conductive pillar and the second conductive pillar from a top gate layer of the gate layers.

Abstract: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.