Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.

Abstract: A computer-implemented method executed by at least one processor for reducing radial distortion errors in fish-eye images is presented. The method includes capturing an image from a camera including distortions, detecting arc-shaped edge segments in the image including the distortions, estimating a main distortion parameter by fixing a distortion centerpoint in a middle of the image, estimating the distortion centerpoint with the main distortion parameter, and obtaining an undistorted version of the captured image by inverting the distortion model.

Abstract: In some embodiments, the present disclosure relates to method of forming an integrated circuit, including forming a semiconductor device on a frontside of a semiconductor substrate; depositing a dielectric layer over a backside of the semiconductor substrate; patterning the dielectric layer to form a first opening in the dielectric layer so that the first opening exposes a surface of the backside of the semiconductor substrate; depositing a glue layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers over the dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, so that the backside contact is coupled to the bonding contacts and the bonding wire layers.

Abstract: There is provided a method of identifying risk of cancer in a human subject, the method comprising: determining in a biological sample of the subject, whether a copy number amplification of at least one continuous genomic region specific to human chromosome 1q21 is present, wherein the presence of a copy number amplification of the region specific to human chromosome 1q21 represents an elevated risk of cancer in the subject and the at least one continuous genomic region is selected from the group consisting of: a human TUFT 1 gene or a gene from the human S100 family. It is also provided a method of treating cancer in a subject determined to have a copy number amplification of a region specific to human chromosome 1q21, the method comprising administering a therapeutic agent capable of suppressing IRAK1, IRAK4 or a S100 family member, such as Pacritinib. There are also provided a method of treating cancer, related polynucleotides, kits, therapeutic agents and use of the therapeutic agents.

Abstract: An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.

Abstract: Systems and methods for demographic determination using image recognition. The method includes analyzing an image with a pre-trained lightweight neural network model, where the lightweight neural network model generates a confidence value, and comparing the confidence value to a threshold value to determine if the pre-trained lightweight neural network model is sufficiently accurate. The method further includes analyzing the image with a pre-trained heavyweight neural network model for the confidence value below the threshold value, wherein the pre-trained heavyweight neural network model has above about one million trainable parameters and the pre-trained lightweight neural network model has a number of trainable parameters below one tenth the heavyweight model, and displaying demographic data to a user on a user interface, wherein the user modifies store inventory based on the demographic data.

Abstract: An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. A guard ring is disposed in the dielectric layer and around the through via. The guard ring includes metal layers stacked along the first direction. The metal layers include first sidewalls and second sidewall. The first sidewalls form an inner sidewall of the guard ring. An overlap between the first sidewalls of the metal layers is less than about 10 nm. The overlap is along a second direction different than the first direction.

Abstract: A method for forming a memory device is provided. The memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

Abstract: Various embodiments described herein provide monitoring and intelligence generation for one or more farm fields by: using remote sensing to monitor progress of a developing crop; comparing a user's field to another field in the area; providing cropped area extent estimates for a current season; using one or more disease risk models to determine disease risk (or disease pressure) with respect to a field; or some combination thereof,

Abstract: A 3D AND flash memory device includes a gate stack structure, a plurality of channel pillars, a plurality of first conductive pillars and a plurality of second conductive pillars, a plurality of charge storage structures, and a plurality of isolation walls. The gate stack structure is located on a dielectric substrate and includes a plurality of gate layers and a plurality of insulating layers alternately stacked on each other. The channel pillars pass through the gate stack structure. The first conductive pillars and the second conductive pillars are located in the channel pillars and are electrically connected to the channel pillars. The charge storage structures are located between the gate layers and the channel pillar. The isolation walls are buried in the gate layers and cover the charge storage structures at outer sidewalls of the second conductive pillars.

Abstract: Methods and systems for deploying a video analytics system include determining one or more applications for a security system in an environment, including one or more constraints. Each functional module in a directed graph representation of one or more applications is profiled to generate one or more configurations for each functional module. The nodes of each graph representation represent functional modules of the respective application, and repeated module configurations are skipped. Resource usage for each of the one or more applications is estimated using the one or more configurations of each functional module and the one or more constraints. The one or more applications are deployed in the environment.

Abstract: A 3D AND flash memory device includes a gate stack structure, a channel pillar, a first and a second conductive pillars, a charge storage structure, and a protective cap. The gate stack structure is disposed on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar penetrates through the gate stack structure. The first and the second conductive pillars are disposed in the channel pillar and penetrate through the gate stack structure, and the first and the second conductive pillars are separated from each other and each connected to the channel pillar. The charge storage structure is disposed between the gate layers and a sidewall of the channel pillar. The protective cap covers at least a top surface of the channel pillar and isolates the first conductive pillar and the second conductive pillar from a top gate layer of the gate layers.

Abstract: At least one shielding layer made of conductive material is formed on a body of a magnetic device to prevent magnetic fields from leaking to the outside of the magnetic device so as to reduce EMI and the size of the magnetic device.

Abstract: An image sensor includes a substrate including a first surface and a second surface opposite to the first surface; a plurality of pixel sensors disposed in the substrate, a sensor isolation feature disposed in the substrate defining an active region, and a dielectric layer between the sensor isolation feature and the substrate, wherein the sensor isolation feature comprises a conductive material.

Abstract: A memory device is provided. The memory device includes a substrate, a stacked structure, and a contact. The substrate includes a memory array region and a staircase region. The stacked structure is located on the substrate in the memory array region and the staircase region. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked on each other. Each of the plurality of conductive layers includes a main body and an end part. The main body is located in the memory array region and extends to the staircase region. The end part is connected to the main body and is located in the staircase region. A thickness of the end part is greater than a thickness of the main body. The contact lands on and is connected to the end part.

Abstract: A coupled inductor has two pillars that are aligned in a vertical direction, wherein a first coil and a second coil are respectively wound around one of the two pillars, respectively, wherein the bottom surface of winding turns of the first coil and the bottom surface of winding turns of the second coil are separated by a gap, wherein a magnetic material is disposed in the gap and a straight line that is enclosed by each of the first coil and the second coil passes through the two pillars.

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a gate stack over a front surface of a substrate. A mask layer is formed over at least a portion of the gate stack and a portion of the front surface. A plurality of dopants are implanted into one or more regions of the substrate that are not covered by the mask layer to form one or more doped isolation features in the substrate. The one or more doped isolation features are formed to have a convex portion at least partially under the gate stack.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region.

Abstract: Some embodiments relate to a method. In the method, semiconductor devices are formed on a frontside of a semiconductor substrate. A trench is formed in a backside of the semiconductor substrate. Conductive and insulating layers are alternatingly formed in the trench on the backside of the semiconductor substrate to establish a backside capacitor. A backside interconnect structure is formed on the backside of the semiconductor substrate to couple to capacitor electrodes of the backside capacitor.

Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.