Patents by Inventor Min Feng

Min Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hybrid bonding technology for stacking integrated circuits
    Patent number: 10727205
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih-Han Huang, I-Nan Chen
  • LAMP DEVICE
    Publication number: 20200208802
    Abstract: A lamp device includes a light emitting unit and a reflecting unit including first and second reflecting modules. The first reflecting module reflects light towards the second reflecting module and has a reflectivity substantially over 70% for light of wavelength ranging from 550 nm to 800 nm. The second reflecting module reflects light towards the first reflecting module and has a reflectivity that substantially ranges from 50% to 75% for light of wavelength ranging from 460 nm to 700 nm. The light emitting unit emits light toward the reflecting unit such that at least a part of the light emitted by the light emitting unit is reflected from one of the first reflecting module and the second reflecting module.
    Type: Application
    Filed: June 3, 2019
    Publication date: July 2, 2020
    Applicant: T.Y.C. BROTHER INDUSTRIAL CO., LTD.
    Inventors: Min-Feng LIN, Nan-Ming LIN
  • Stacked semiconductor dies with a conductive feature passing through a passivation layer
    Patent number: 10680027
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang
  • STRUCTURE FOR STANDARD LOGIC PERFORMANCE IMPROVEMENT HAVING A BACK-SIDE THROUGH-SUBSTRATE-VIA
    Publication number: 20200161244
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate. A conductive pad is arranged along a back-side of the first substrate and a first through-substrate-via (TSV) extends between an interconnect wire of the first plurality of interconnect layers and the conductive pad. A second plurality of interconnect layers are within a second ILD structure disposed along a front-side of a second substrate that is bonded to the first substrate. A second through substrate via (TSV) extends through the second substrate. The second TSV has a greater width than the first TSV.
    Type: Application
    Filed: December 11, 2019
    Publication date: May 21, 2020
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang
  • Interconnect Structure for Stacked Device and Method
    Publication number: 20200127027
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Application
    Filed: December 20, 2019
    Publication date: April 23, 2020
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • LAMP COVER
    Publication number: 20200116328
    Abstract: A lamp cover adapted for mounting to a vehicle lamp having an optical axis includes a light-transmissible cover body, an electrically-conductive film being light-transmissible and being formed on the cover body, and an electrode unit being electrically connected to the electrically-conductive film. The electrically-conductive film is adapted for converting electrical energy provided by the electrode unit into thermal energy to heat the cover body.
    Type: Application
    Filed: May 8, 2019
    Publication date: April 16, 2020
    Applicant: T.Y.C. BROTHER INDUSTRIAL CO., LTD.
    Inventors: Min-Feng LIN, Nan-Ming LIN
  • Semiconductor structure, back-side illuminated image sensor and method for manufacturing the same
    Patent number: 10622401
    Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sheng-Chau Chen, Cheng-Hsien Chou, Min-Feng Kao
  • Gate Electrodes with Notches and Methods for Forming the Same
    Publication number: 20200083049
    Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventors: Min-Feng Kao, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Feng-Chi Hung
  • Structure and Method for 3D Image Sensor
    Publication number: 20200075659
    Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jen-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Semiconductor Switching Device Separated by Device Isolation
    Publication number: 20200066774
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • INTEGRATED CIRCUIT (IC) STRUCTURE FOR HIGH PERFORMANCE AND FUNCTIONAL DENSITY
    Publication number: 20200066584
    Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 27, 2020
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Kuan-Chieh Huang
  • Hybrid bonding technology for stacking integrated circuits
    Publication number: 20200058617
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
    Type: Application
    Filed: August 15, 2018
    Publication date: February 20, 2020
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih Han Huang, I-Nan Chen
  • Structure for standard logic performance improvement having a back-side through-substrate-via
    Patent number: 10566288
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of interconnect layers within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate and a conductive bond pad is separated from the substrate by the dielectric layer. A back-side through-substrate-via (BTSV) extends through the substrate and the dielectric layer. A conductive bump is arranged over the conductive bond pad. The conductive bond pad has a substantially planar lower surface extending from over the BTSV to below the conductive bump. A BTSV liner separates sidewalls of the BTSV from the substrate. The sidewalls of the BTSV directly contact sides of both the BTSV liner and the dielectric layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: February 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang
  • INTEGRATED CIRCUIT (IC) STRUCTURE FOR HIGH PERFORMANCE AND FUNCTIONAL DENSITY
    Publication number: 20200043783
    Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Kuan-Chieh Huang
  • INDUCTOR STRUCTURE FOR INTEGRATED CIRCUIT
    Publication number: 20200027789
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • INDUCTOR STRUCTURE FOR INTEGRATED CIRCUIT
    Publication number: 20200027790
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Interconnect structure for stacked device and method
    Patent number: 10535706
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Tzu-Hsuan Hsu, Shu-Ting Tsai, Min-Feng Kao
  • Structure and method for 3D Image sensor
    Patent number: 10535697
    Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jen-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Vehicle light assembly
    Patent number: 10527253
    Abstract: A vehicle light assembly includes a lens unit, a lens cover, a heat dissipation seat, a clamp and a plurality of fasteners. The lens cover is connected to the lens unit. The heat dissipation seat is disposed rearward of the lens unit and the lens cover. The clamp is connected to a front side of the heat dissipation seat and defines a clamping space receiving the lens unit and the lens cover. The clamp clamps tightly the lens cover against the lens unit. The fasteners are threaded forwardly into the lens cover from a rear side of the dissipation seat.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: January 7, 2020
    Assignee: T.Y.C. BROTHER INDUSTRIAL CO., LTD.
    Inventors: Min-Feng Lin, Yu-Bin Thao, Shih-Ting Tsai
  • Semiconductor devices, methods of manufacturing thereof, and image sensor devices
    Patent number: 10515994
    Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Feng-Chi Hung, Min-Feng Kao