Abstract: A filter device with a spirally flushing function with a head having a filter flask main body and a water inlet hole connected with a water inlet passage, a water outlet hole connected with a water outlet passage, and a flushing hole connected with a flushing passage. A filter element casing arranged outside the filter element, and has a plurality of filter element casing water inlets. A flow divider arranged outside the filter element casing and covering a portion of an upper end of the filter element casing. A filter element end cap fixed to the top of the filter element and having a water outlet, which penetrates through the flow divider and is connected with the water outlet passage. Effectively improved flushing effect, and greatly prolonged service life of the filter element is experienced.

Abstract: The present disclosure relates to a method of forming a semiconductor device structure. The method may be performed by forming a gate structure along a first side of a semiconductor substrate. The semiconductor substrate is thinned. Thinning the semiconductor substrate causes defects to form along a second side of the semiconductor substrate opposing the first side of the semiconductor substrate. Dopants are implanted into the second side of the semiconductor substrate after thinning the semiconductor substrate. The semiconductor substrate is annealed to form a doped layer after implanting the dopants. The doped layer is formed along the second side of the semiconductor substrate.

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a standard via disposed on a first side of a substrate. An oversized via is disposed on the first side of the substrate and is laterally separated from the standard via. The oversized via has a larger width than the standard via. An interconnect wire vertically contacting the oversized via. A through-substrate via (TSV) extends from a second side of the substrate, and through the substrate, to physically contact the oversized via or the interconnect wire. The TSV has a minimum width that is smaller than a width of the oversized via.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: A method for free flow fever screening is presented. The method includes capturing a plurality of frames from thermal data streams and visual data streams related to a same scene to define thermal data frames and visual data frames, detecting and tracking a plurality of individuals moving in a free-flow setting within the visual data frames, and generating a tracking identification for each individual of the plurality of individuals present in a field-of-view of the one or more cameras across several frames of the plurality of frames. The method further includes fusing the thermal data frames and the visual data frames, measuring, by a fever-screener, a temperature of each individual of the plurality of individuals within and across the plurality of frames derived from the thermal data streams and the visual data streams, and generating a notification when a temperature of an individual exceeds a predetermined threshold temperature.

Abstract: A memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

Abstract: In some embodiments, the present disclosure relates to a three dimensional (3D) integrated circuit (IC) stack, including a first IC die having a first substrate and a first interconnect structure over a frontside of the first substrate; a second IC die having a second substrate and a second interconnect structure over the frontside of the second substrate; and a third IC die vertically between the first and second IC dies and having a third substrate, a third interconnect structure over the frontside of the third substrate, and a third bonding structure over a backside of the third substrate. A heat dissipation path extends from the third substrate to at least the first or second substrate, and includes a backside contact that extends from the third bonding structure to the backside of the third substrate and that is thermally coupled to at least the first or second interconnect structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnects within a first inter-level dielectric (ILD) structure disposed along a first side of a first substrate. A conductive pad is arranged along a second side of the first substrate. A first through-substrate-via (TSV) physically contacts an interconnect of the first plurality of interconnects and a first surface of the conductive pad. A second plurality of interconnects are within a second ILD structure disposed on a second substrate. A second TSV extends from an interconnect of the second plurality of interconnects to through the second substrate. A conductive bump is arranged on a second surface of the conductive pad opposing the first surface. The second TSV has a greater width than the first TSV.

Abstract: Systems and methods to specify and execute real-time streaming applications are provided. The method includes specifying an application topology for an application including spouts, bolts, connections, a global hash table, and a topology manager. Each spout receives input data and each bolt transforms the input data, the global hash table allows in memory communication between each spout and bolt to others of the spouts and the bolts. The topology manager manages the application topology. The method includes compiling the application into a shared or static library for applications, and exporting a special symbol associated with the application. The runtime system can be used to retrieve the application topology from the shared or static library based on the special symbol and execute the application topology on a single node or distribute across multiple nodes.

Abstract: Systems and methods are disclosed for distributed real-time security monitoring and alerting. The methods include transmitting a selected portion of biometrics data as a watchlist to each worker unit. The portion of biometrics data is selected in response to respective characteristic data received from each worker unit. Facial recognition data is received from each worker unit. The facial recognition data includes a person of interest with an associated match confidence value calculated by each worker unit based on respective watchlists received by each worker unit. A combined match confidence value is calculated between a same person of interest identified in multiple facial recognition data received from each worker unit and the biometric data associated with an individual. The combined match confidence value is calculated in response to match confidence values associated with the same person of interest in respective facial recognition data being below a match confidence threshold.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.

Abstract: A computer-implemented method includes obtaining a usecase specification and a usecase runtime specification corresponding to the usecase. The usecase includes a plurality of applications each being associated with a micro-service providing a corresponding functionality within the usecase for performing a task. The method further includes managing execution of the usecase within a runtime system based on the usecase and usecase runtime specifications to perform the task by serving an on-demand query and dynamically scaling resources based on the on-demand query, including using a batch helper server to employ the usecase specification to load dynamic application instances and connect the dynamic application instances to existing instances, and employ a batch helper configuration to load nodes/machines for execution of the on-demand query.

Abstract: A computer-implemented method executed by at least one processor for reducing radial distortion errors in fish-eye images is presented. The method includes capturing an image from a camera including distortions, detecting arc-shaped edge segments in the image including the distortions, estimating a main distortion parameter by fixing a distortion centerpoint in a middle of the image, estimating the distortion centerpoint with the main distortion parameter, and obtaining an undistorted version of the captured image by inverting the distortion model.

Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate. A conductive pad is arranged along a back-side of the first substrate and a first through-substrate-via (TSV) extends between an interconnect wire of the first plurality of interconnect layers and the conductive pad. A second plurality of interconnect layers are within a second ILD structure disposed along a front-side of a second substrate that is bonded to the first substrate. A second through substrate via (TSV) extends through the second substrate. The second TSV has a greater width than the first TSV.

Abstract: Systems and methods for demographic determination using image recognition. The method includes analyzing an image with a pre-trained lightweight neural network model, where the lightweight neural network model generates a confidence value, and comparing the confidence value to a threshold value to determine if the pre-trained lightweight neural network model is sufficiently accurate. The method further includes analyzing the image with a pre-trained heavyweight neural network model for the confidence value below the threshold value, wherein the pre-trained heavyweight neural network model has above about one million trainable parameters and the pre-trained lightweight neural network model has a number of trainable parameters below one tenth the heavyweight model, and displaying demographic data to a user on a user interface, wherein the user modifies store inventory based on the demographic data.

Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.