Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

Abstract: A semiconductor device structure is provided. The semiconductor device structure has a first surface and a second surface. A first charged layer is disposed over the second surface. A dielectric layer separates a surface of the first charged layer that is closest to the semiconductor substrate from the second surface of the semiconductor substrate. A second charged layer is over the first charged layer. The first charged layer and the second charged layer are different materials and have a same charge polarity.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.

Abstract: A coating layer is formed on a coil made of an insulated conductive wire comprising a metal wire and an insulating layer encapsulating the metal layer, wherein the coating layer encapsulates at least one portion of the insulating layer of the insulated conductive wire so that a terminal part of the metal wire exposed from the insulating layer can be positioned firmly while going through an automatic soldering process for electrically connecting with an external circuit.

Abstract: A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

Abstract: An inductor array comprising a magnetic body and a plurality of coils disposed in the magnetic body, wherein the magnetic body comprises a unitary portion that is disposed over and across the plurality of coils and extended into a space between each two adjacent coils of the plurality of coils.

Abstract: A computer-implemented method includes obtaining a usecase specification and a usecase runtime specification corresponding to the usecase. The usecase includes a plurality of applications each being associated with a micro-service providing a corresponding functionality within the usecase for performing a task. The method further includes determining that at least one instance of the at least one of the plurality of applications can be reused during execution of the usecase based on the usecase specification and the usecase runtime specification, and reusing the at least one instance during execution of the usecase.

Abstract: Methods and systems for authentication include determining, at a first worker system, that a master system that stores a current authentication-list cannot be reached by a first network. Authentication is performed on an authentication request using a previously stored copy of the authentication-list at the first worker system. The authentication includes facial recognition that is performed on detected face images for a first time window, before receiving the authentication request, and for a second time window, after receiving the authentication request. Authentication removes matching detected face images after completing an authentication request to prevent other individuals from using a same identifier. Access is granted to a secured area responsive to the authentication.

Abstract: Methods and systems for deploying a video analytics system include determining one or more applications for a security system in an environment, including one or more constraints. Each functional module in a directed graph representation of one or more applications is profiled to generate one or more configurations for each functional module. The nodes of each graph representation represent functional modules of the respective application, and repeated module configurations are skipped. Resource usage for each of the one or more applications is estimated using the one or more configurations of each functional module and the one or more constraints. The one or more applications are deployed in the environment.

Abstract: A computer-implemented method includes obtaining a usecase specification and a usecase runtime specification corresponding to the usecase. The usecase includes a plurality of applications each being associated with a micro-service providing a corresponding functionality within the usecase for performing a task. The method further includes managing execution of the usecase within a runtime system based on the usecase and usecase runtime specifications to perform the task by serving an on-demand query and dynamically scaling resources based on the on-demand query, including using a batch helper server to employ the usecase specification to load dynamic application instances and connect the dynamic application instances to existing instances, and employ a batch helper configuration to load nodes/machines for execution of the on-demand query.

Abstract: Systems and methods are disclosed for distributed real-time security monitoring and alerting. The methods include transmitting a selected portion of biometrics data as a watchlist to each worker unit. The portion of biometrics data is selected in response to respective characteristic data received from each worker unit. Facial recognition data is received from each worker unit. The facial recognition data includes a person of interest with an associated match confidence value calculated by each worker unit based on respective watchlists received by each worker unit. A combined match confidence value is calculated between a same person of interest identified in multiple facial recognition data received from each worker unit and the biometric data associated with an individual. The combined match confidence value is calculated in response to match confidence values associated with the same person of interest in respective facial recognition data being below a match confidence threshold.

Abstract: Systems and methods to specify and execute real-time streaming applications are provided. The method includes specifying an application topology for an application including spouts, bolts, connections, a global hash table, and a topology manager. Each spout receives input data and each bolt transforms the input data, the global hash table allows in memory communication between each spout and bolt to others of the spouts and the bolts. The topology manager manages the application topology. The method includes compiling the application into a shared or static library for applications, and exporting a special symbol associated with the application. The runtime system can be used to retrieve the application topology from the shared or static library based on the special symbol and execute the application topology on a single node or distribute across multiple nodes.

Abstract: A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device has a gate stack arranged over a first surface of a substrate. A doped isolation feature is arranged within the substrate along opposing sides of the gate stack. A photodetector is also arranged within the substrate. An isolation well region extends below the gate stack and contacts the doped isolation feature along a horizontal plane that is parallel to the first surface and that intersects sides of the photodetector.

Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer in proximity to the active side of the semiconductor substrate, and a through substrate via extending from the semiconductor substrate to a first metal layer of the interconnect layer. The TSV being wider than the continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.