Abstract: Provided is a current-voltage conversion amplifier circuit including: a plurality of light receiving devices generating a current signal proportional to an amount of light by receiving the light; multipliers amplifying the current signal, converting the amplified current signal into a first voltage signal, outputting the amplified current signal, or outputting the converted first voltage signal; multi input amplifiers outputting first and second output voltage pairs through a process for receiving output values of multipliers and an offset voltage and amplifying the received output values and offset voltage; a multiplexing unit selecting and outputting one first and second output voltage pair among the first and second output voltage pairs outputted from multi input amplifiers; and a signal conversion unit converting a difference value between first and second output voltages outputted from the multiplexing unit and outputting the converted digital signal.

Abstract: Provided is a wheel speed sensor interface. The wheel speed sensor interface includes: a speed pulse detection circuit configured to receive a plurality of sensor signals including wheel speed information of a vehicle, detect a plurality of speed pulses on the basis of the plurality of the received sensor signals, and transmit the plurality of the detected speed pulses to an external device; and a comparison speed detection circuit configured to generate a plurality of counting values by counting each of the detected speed pulses, generate comparison speed information by multiplexing the plurality of the generated counting values through a time division method, and transmit the generated comparison speed information to the external device.

Abstract: The present invention relates to a system and method for providing additional information using image matching. The present invention provides a system for providing additional information using image matching, including: a image input unit configured to receive a video or an image input from a user terminal; a query image determination unit configured to determine a query image, i.e.

Abstract: Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current.

Abstract: Provided is a capacitor-type sensor read-out circuit. The capacitor-type sensor read-out circuit includes: a signal conversion unit outputting a sensor signal inputted from a sensor; a voltage booster generating a bias voltage; and a capacitor-type signal coupling circuit receiving the sensor signal as a feedback, mixing the received sensor signal with the bias voltage, and outputting the mixed signal.

Abstract: Provided is a wheel speed sensor interface. The wheel speed sensor interface includes: a speed pulse detection circuit configured to receive a plurality of sensor signals including wheel speed information of a vehicle, detect a plurality of speed pulses on the basis of the plurality of the received sensor signals, and transmit the plurality of the detected speed pulses to an external device; and a comparison speed detection circuit configured to generate a plurality of counting values by counting each of the detected speed pulses, generate comparison speed information by multiplexing the plurality of the generated counting values through a time division method, and transmit the generated comparison speed information to the external device.

Abstract: An MEMS microphone is provided which includes a reference voltage/current generator configured to generate a DC reference voltage and a reference current; a first noise filter configured to remove a noise of the DC reference voltage; a voltage booster configured to generate a sensor bias voltage using the DC reference voltage the noise of which is removed; a microphone sensor configured to receive the sensor bias voltage and to generate an output value based on a variation in a sound pressure; a bias circuit configured to receive the reference current to generate a bias voltage; and a signal amplification unit configured to receive the bias voltage and the output value of the microphone sensor to amplify the output value. The first noise filter comprises an impedance circuit; a capacitor circuit connected to a output node of the impedance circuit; and a switch connected to both ends of the impedance circuit.

Abstract: Provided is a readout integrated circuit including a sensor signal processing unit receiving sensor signals from a plurality of sensors and converting respectively the sensor signals into voltage signals, a signal converting unit respectively converting the voltage signals into digital signals, a digital signal processing unit outputting digital signals processed in response to the voltage signals and a switching control signal, a power supplying unit generating an internal voltage for operating the signal converting unit and the digital signal processing unit, and a reference sensing voltage for operating the sensor signal processing unit, and a switch unit operating in response to the switching control signal, wherein the switch unit includes switches respectively corresponding to the plurality of sensors and a current amount applied to each sensor is adjusted in response to operation times of the switches.

Abstract: Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.

Abstract: Provided are a current switch driving circuit generating a signal for driving a current switch, and a digital-to-analog converter using the same. The current switch driving circuit includes a first PMOS transistor in which a source terminal is connected to a power supply terminal, a gate terminal receives an input signal, and a drain terminal outputs a driving signal, an NMOS transistor in which a drain terminal is connected to the drain terminal of the first PMOS transistor, and a gate terminal receives the input signal, a second PMOS transistor in which a source terminal is connected to a source terminal of the NMOS transistor, a gate terminal is connected to a bias voltage terminal, and a drain terminal is connected to a ground terminal, and a control current source allowing the second PMOS transistor to be maintained constantly in an ON state.

Abstract: Provided is a clock timing adjustment device for adjusting a time difference of clocks and a delta-sigma modulator. The clock timing adjustment device includes a power detection unit and a timing adjustment unit. The power detection unit receives input signals which are generated using pairs of first and second clocks having a plurality of clock time differences and respectively correspond to the clock time differences, detects powers of the input signals, and outputs a control signal corresponding to a clock time difference where the power is minimized. The timing adjustment unit receives a reference clock and the control signal and outputs the first and second clocks having the clock time difference where the power is minimized from the reference clock according to the control signal.

Abstract: Provided is a voltage supply circuit using a charge pump. The voltage supply circuit enhances charge pump output voltage fluctuation characteristics depending on load variation of a charge pump voltage generator (load regulation characteristics) when receiving an operation power supply voltage of the charge pump through a regulator. The voltage supply circuit is configured to feed back fluctuation of a charge pump output voltage to a charge pump voltage regulator. The fluctuation of the charge pump output voltage is compensated through fluctuation of an output voltage of the charge pump to active enhance the load regulation characteristics.

Abstract: Disclosed is a sound detecting circuit which includes a sensing unit configured to generate an AC signal in response to a sound pressure level of a sound signal; an amplification unit configured to amplify the AC signal; and a bias voltage generating unit configured to generate a bias voltage to be provided to the amplification unit. The bias voltage generating unit comprises a current source configured to provide a power current; and a current-voltage converting circuit configured to convert the power current into the bias voltage and to reduce a noise due to the power current.

Abstract: Provided is a read-out circuit that is connected to a microphone and configured to linearly amplify a current signal generated by the microphone and output the amplified current signal. The read-out circuit includes an amplification unit and a feedback resistor. The amplification unit has an amplification gain between 0 and 1. The feedback resistor is connected between input and output terminals of the amplification unit. As the amplification gain of the amplification unit becomes closer to 1, an input impedance becomes higher. A preamp of the read-out circuit can have a high input impedance due to the amplification gain, and the read-out circuit can be manufactured using a CMOS process.

Abstract: Provided are a current switch driving circuit generating a signal for driving a current switch, and a digital-to-analog converter using the same. The current switch driving circuit includes a first PMOS transistor in which a source terminal is connected to a power supply terminal, a gate terminal receives an input signal, and a drain terminal outputs a driving signal, an NMOS transistor in which a drain terminal is connected to the drain terminal of the first PMOS transistor, and a gate terminal receives the input signal, a second PMOS transistor in which a source terminal is connected to a source terminal of the NMOS transistor, a gate terminal is connected to a bias voltage terminal, and a drain terminal is connected to a ground terminal, and a control current source allowing the second PMOS transistor to be maintained constantly in an ON state.

Abstract: Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.

Abstract: Provided are an active resistance-capacitance (RC) integrator and a continuous-time sigma-delta modulator, which have a gain control function. The active RC integrator includes an amplifier, a first base resistor connected between a first input node and a positive input port of the amplifier, a second base resistor connected between a second input node and a negative input port of the amplifier, a first resistor unit connected between the second input node and the positive input port of the amplifier, and a second resistor unit connected between the first input node and the negative input port of the amplifier. A resistor network including resistors and switches is configured to vary an input resistance, so that an active RC integrator may have a gain control function.

Abstract: Provided is a clock timing adjustment device for adjusting a time difference of clocks and a delta-sigma modulator. The clock timing adjustment device includes a power detection unit and a timing adjustment unit. The power detection unit receives input signals which are generated using pairs of first and second clocks having a plurality of clock time differences and respectively correspond to the clock time differences, detects powers of the input signals, and outputs a control signal corresponding to a clock time difference where the power is minimized. The timing adjustment unit receives a reference clock and the control signal and outputs the first and second clocks having the clock time difference where the power is minimized from the reference clock according to the control signal.

Abstract: Provided are a coefficient multiplier and digital delta-sigma modulator using the same. The coefficient multiplier has the average of output signals of respective dependent multipliers as an effective coefficient using a coefficient averaging technique without employing an adder that has a complex structure and occupies a large chip area. Accordingly, the coefficient multiplier has a simple hardware constitution and small chip area in comparison with a canonical signed digit (CSD) coefficient multiplier, and the digital delta-sigma modulator employing the coefficient multiplier has a simple structure and small size.

Abstract: Provided are a coefficient multiplier and digital delta-sigma modulator using the same. The coefficient multiplier has the average of output signals of respective dependent multipliers as an effective coefficient using a coefficient averaging technique without employing an adder that has a complex structure and occupies a large chip area. Accordingly, the coefficient multiplier has a simple hardware constitution and small chip area in comparison with a canonical signed digit (CSD) coefficient multiplier, and the digital delta-sigma modulator employing the coefficient multiplier has a simple structure and small size.