Patents by Inventor Min-Lin Lee

Min-Lin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961938
    Abstract: A method of processing light-emitting elements includes: transferring a plurality of light-emitting elements from original wafers or next-stage carriers, based on a predetermined pattern. The predetermined pattern arranges two adjacent LED groups in a first direction on the original wafer or carriers to be placed on two non-adjacent positions in the first direction on the next-stage carriers. The light-emitting elements on the original wafer have a horizontal wafer pitch and a vertical wafer pitch. The light-emitting elements on each of the next-stage carriers have a first horizontal pitch and a first vertical pitch. The first horizontal pitch is greater than the horizontal wafer pitch, or the first vertical pitch is greater than the vertical wafer pitch. Besides, a light-emitting element device using the aforementioned method is also provided.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 16, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Chang-Lin Lee
  • Publication number: 20230189435
    Abstract: A circuit board and an electronic package using the same are provided. The circuit board includes a rigid board body, at least one bendable extension portion, connecting members, and shielding members. The rigid board body includes conductive layers and dielectric layers therebetween. The extension portion is connected to a side of the rigid board body and formed by layers of the conductive layers and at least one layer of the dielectric layers extending outside the rigid board body. The connecting members are arranged on a connecting end of the extension portion and electrically connected to a signal layer of the conductive layers. The shielding members are arranged around the corresponding connecting members and electrically connected to a ground layer of the conductive layers. The connecting members and the shielding members protrude from the connecting end. A height of the shielding members is lower than a height of the connecting members.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 15, 2023
    Applicants: First Hi-tec Enterprise Co.,Ltd., NEXCOM International Co., Ltd., Industrial Technology Research Institute
    Inventors: Min-Lin Lee, Sheng-Che Hung, Ching-Shan Chang, Ying-Tsuen Liou
  • Patent number: 10559534
    Abstract: A circuit substrate includes a dielectric layer, a first conductive structure and a second conductive structure. The first conductive structure includes a first conductive circuit and a first conductive via. The first conductive circuit is disposed on the dielectric layer. The first conductive via is disposed in the dielectric layer, and the first conductive circuit is connected to the first conductive via. The second conductive structure includes a second conductive circuit and a second conductive via. The second conductive circuit is disposed in the dielectric layer, the second conductive circuit and the first conductive circuit of the first conductive structure are arranged with an interval, and the second conductive via surrounds the first conductive via with an interval. The second conductive structure has an extending portion. The extending portion protrudes toward the first conductive via and does not contact the first conductive via.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: February 11, 2020
    Assignees: Industrial Technology Research Institute, First Hi-tec Enterprise Co., Ltd., NEXCOM International Co., Ltd.
    Inventors: Sheng-Che Hung, Min-Lin Lee, Ching-Shan Chang, Hung-I Liu
  • Publication number: 20190148300
    Abstract: A circuit substrate includes a dielectric layer, a first conductive structure and a second conductive structure. The first conductive structure includes a first conductive circuit and a first conductive via. The first conductive circuit is disposed on the dielectric layer. The first conductive via is disposed in the dielectric layer, and the first conductive circuit is connected to the first conductive via. The second conductive structure includes a second conductive circuit and a second conductive via. The second conductive circuit is disposed in the dielectric layer, the second conductive circuit and the first conductive circuit of the first conductive structure are arranged with an interval, and the second conductive via surrounds the first conductive via with an interval. The second conductive structure has an extending portion. The extending portion protrudes toward the first conductive via and does not contact the first conductive via.
    Type: Application
    Filed: August 2, 2018
    Publication date: May 16, 2019
    Applicants: Industrial Technology Research Institute, First Hi-tec Enterprise Co.,Ltd., NEXCOM International Co., Ltd.
    Inventors: Sheng-Che Hung, Min-Lin Lee, Ching-Shan Chang, Hung-I Liu
  • Patent number: 10129974
    Abstract: A multi-layer circuit structure includes a differential transmission line pair and at least one conductive pattern. The differential transmission line pair includes first and second transmission lines disposed side by side. Each of the first and second transmission lines includes first and second segments connected to each other. An spacing between the two first segments is non-fixed, and an spacing between the two second segments is fixed. A first zone is located between the two first segments, a second zone is opposite to the first zone and located outside the first segment of the first transmission line, and a third zone is opposite to the first zone and located outside the first segment of the second transmission line. The conductive pattern is coplanar with the differential transmission line pair and disposed on at least one of the first, second and third zones.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: November 13, 2018
    Assignees: Industrial Technology Research Institute, First Hi-tec Enterprise Co., Ltd., NEXCOM International Co., Ltd.
    Inventors: Chien-Min Hsu, Min-Lin Lee, Huey-Ru Chang, Hung-I Liu, Ching-shan Chang
  • Publication number: 20170273174
    Abstract: A multi-layer circuit structure includes a differential transmission line pair and at least one conductive pattern. The differential transmission line pair includes first and second transmission lines disposed side by side. Each of the first and second transmission lines includes first and second segments connected to each other. An spacing between the two first segments is non-fixed, and an spacing between the two second segments is fixed. A first zone is located between the two first segments, a second zone is opposite to the first zone and located outside the first segment of the first transmission line, and a third zone is opposite to the first zone and located outside the first segment of the second transmission line. The conductive pattern is coplanar with the differential transmission line pair and disposed on at least one of the first, second and third zones.
    Type: Application
    Filed: August 24, 2016
    Publication date: September 21, 2017
    Applicants: Industrial Technology Research Institute, First Hi-tec Enterprise Co.,Ltd., NEXCOM International Co., Ltd.
    Inventors: Chien-Min Hsu, Min-Lin Lee, Huey-Ru Chang, Hung-I Liu, Ching-shan Chang
  • Patent number: 9706656
    Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 11, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Min Hsu, Shih-Hsien Wu, Jing-Yao Chang, Tao-Chih Chang, Ren-Shin Cheng, Min-Lin Lee
  • Publication number: 20160174360
    Abstract: A signal transmission board includes a substrate, a conductive via, a cavity and a connecting hole. The substrate has a first external surface and a second external surface. The conductive via penetrating through the substrate has a first end and a second end. The first end is disposed on the first external surface, and the second end is disposed on the second external surface. The cavity is disposed in the substrate and penetrated by the conductive via. The connecting hole disposed on the substrate has a third end and a fourth end. The third end is disposed on the first external surface, and the fourth end communicates with the cavity.
    Type: Application
    Filed: November 24, 2015
    Publication date: June 16, 2016
    Inventors: Chien-Min HSU, Shih-Hsien WU, Jing-Yao CHANG, Tao-Chih CHANG, Ren-Shin CHENG, Min-Lin LEE
  • Patent number: 9258883
    Abstract: A via structure includes a ground conductor, a floated conductor and a signal conductor. The ground conductor is electrically coupled to a reference potential. The floated conductor is electrically insulated from the ground conductor. The signal conductor is located between and insulated from the ground conductor and the floated conductor.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: February 9, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Hsien Wu, Min-Lin Lee
  • Publication number: 20150334821
    Abstract: A via structure includes a ground conductor, a floated conductor and a signal conductor. The ground conductor is electrically coupled to a reference potential. The floated conductor is electrically insulated from the ground conductor. The signal conductor is located between and insulated from the ground conductor and the floated conductor.
    Type: Application
    Filed: July 27, 2015
    Publication date: November 19, 2015
    Inventors: Shih-Hsien WU, Min-Lin Lee
  • Patent number: 9125304
    Abstract: The disclosure provides a manufacturing method for a circuit board having a via and including a substrate, a ground conductor, a floated conductor and a signal conductor. The substrate includes a second sheet layer, a second ground layer, a core layer, a first ground layer and a first sheet layer that are stacked in sequence from bottom to top. The ground conductor penetrates through the core layer and is electrically coupled to the first ground layer and the second ground layer. The floated conductor penetrates through the core layer and is electrically insulated from the first ground layer, the second ground layer and the ground conductor. The signal conductor penetrates through the substrate, being located between the ground conductor and the floated conductor, and insulated from the first ground layer, the second ground layer, the ground conductor and the floated conductor.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: September 1, 2015
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Hsien Wu, Min-Lin Lee
  • Publication number: 20150181693
    Abstract: The disclosure provides a manufacturing method for a circuit board having a via and including a substrate, a ground conductor, a floated conductor and a signal conductor. The substrate includes a second sheet layer, a second ground layer, a core layer, a first ground layer and a first sheet layer that are stacked in sequence from bottom to top. The ground conductor penetrates through the core layer and is electrically coupled to the first ground layer and the second ground layer. The floated conductor penetrates through the core layer and is electrically insulated from the first ground layer, the second ground layer and the ground conductor. The signal conductor penetrates through the substrate, being located between the ground conductor and the floated conductor, and insulated from the first ground layer, the second ground layer, the ground conductor and the floated conductor.
    Type: Application
    Filed: March 26, 2014
    Publication date: June 25, 2015
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Hsien WU, Min-Lin LEE
  • Patent number: 9029984
    Abstract: A semiconductor substrate assembly is proposed. The semiconductor interposer comprises a substrate having a first surface and a second surface opposite to the first surface, a first conductive pad, a second conductive pad and a conductive pillar. The first conductive pad is formed at a predetermined location of the first surface of the substrate. The second conductive pad is formed at a predetermined location of the second surface of the substrate as compared with the position of the first conductive pad. The conductive pillar is formed in the substrate and contacts with one of the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 12, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Peng-Shu Chen, Min-Lin Lee, Shih-Hsien Wu, Shur-Fen Liu
  • Patent number: 9030808
    Abstract: A capacitor and a circuit board having the same are provided. The capacitor includes a substrate, an oxide layer, a second electrode, an insulating layer, a plurality of conductive sheets and a plurality of vias. The substrate includes a first electrode and a porous structure. The porous structure in at least of two distribution regions has different depths. An oxide layer is disposed on the surface of the porous structure. The second electrode is disposed on the oxide layer and includes a conductive polymer material. The insulating layer disposed on the second electrode has a third and a fourth surfaces. The fourth surface of the insulating layer is connected with the second electrode. The conductive sheets are disposed on the first surface of the first electrode and the third surface of the insulating layer and electrically connected with the corresponding vias according to different polarities.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 12, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Li-Duan Tsai
  • Patent number: 9013893
    Abstract: An embedded capacitor module includes an electrode lead-out portion and at least one solid electrolytic capacitor portion adjacently disposed with the electrode lead-out portion. The electrode lead-out portion comprises a first substrate, a second substrate, a first insulating material disposed between the first substrate and the second substrate, a first porous layer formed on at least one surface of the first substrate, and a first oxide layer disposed on the first porous layer. The solid electrolytic capacitor portion comprises the first substrate, the second substrate, the first porous layer, the first oxide layer, all of which are extended from the electrode lead-out portion, a first conductive polymer layer disposed on the first oxide layer, a first carbon layer disposed on the first conductive polymer layer, and a first conductive adhesive layer disposed on the first carbon layer.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: April 21, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Cheng-Liang Cheng, Li-Duan Tsai
  • Patent number: 8941015
    Abstract: An embedded capacitor substrate module includes a substrate, a metal substrate and a solid electrolytic capacitor material. The solid electrolytic capacitor material is formed on the metal substrate, so as to form a solid electrolytic capacitor with the substrate. The embedded capacitor substrate module further includes an electrode lead-out region formed by extending the substrate and the metal substrate. The metal substrate serves as a first electrode, and the substrate serves as a second electrode. An insulating material is formed between the substrate and the metal substrate. Therefore, the embedded capacitor substrate module is not only advantageous in having a large capacitance as the conventional solid capacitor, but also capable of being drilled or plated and electrically connected to other circuits after being embedded in a printed circuit board.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: January 27, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Cheng-Liang Cheng, Li-Duan Tsai
  • Publication number: 20140048908
    Abstract: A semiconductor substrate assembly is proposed. The semiconductor interposer comprises a substrate having a first surface and a second surface opposite to the first surface, a first conductive pad, a second conductive pad and a conductive pillar. The first conductive pad is formed at a predetermined location of the first surface of the substrate. The second conductive pad is formed at a predetermined location of the second surface of the substrate as compared with the position of the first conductive pad. The conductive pillar is formed in the substrate and contacts with one of the first conductive pad and the second conductive pad.
    Type: Application
    Filed: March 12, 2013
    Publication date: February 20, 2014
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Peng-Shu Chen, Min-Lin Lee, Shih-Hsien Wu, Shur-Fen Liu
  • Publication number: 20130248235
    Abstract: An embedded capacitor module includes an electrode lead-out portion and at least one solid electrolytic capacitor portion adjacently disposed with the electrode lead-out portion. The electrode lead-out portion comprises a first substrate, a second substrate, a first insulating material disposed between the first substrate and the second substrate, a first porous layer formed on at least one surface of the first substrate, and a first oxide layer disposed on the first porous layer. The solid electrolytic capacitor portion comprises the first substrate, the second substrate, the first porous layer, the first oxide layer, all of which are extended from the electrode lead-out portion, a first conductive polymer layer disposed on the first oxide layer, a first carbon layer disposed on the first conductive polymer layer, and a first conductive adhesive layer disposed on the first carbon layer.
    Type: Application
    Filed: May 17, 2013
    Publication date: September 26, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Min Hsu, Min-Lin Lee, Cheng-Liang Cheng, Li-Duan Tsai
  • Publication number: 20130233605
    Abstract: A capacitor and a circuit board having the same are provided. The capacitor includes a substrate, an oxide layer, a second electrode, an insulating layer, a plurality of conductive sheets and a plurality of vias. The substrate includes a first electrode and a porous structure. The porous structure in at least of two distribution regions has different depths. An oxide layer is disposed on the surface of the porous structure. The second electrode is disposed on the oxide layer and includes a conductive polymer material. The insulating layer disposed on the second electrode has a third and a fourth surfaces. The fourth surface of the insulating layer is connected with the second electrode. The conductive sheets are disposed on the first surface of the first electrode and the third surface of the insulating layer and electrically connected with the corresponding vias according to different polarities.
    Type: Application
    Filed: September 10, 2012
    Publication date: September 12, 2013
    Applicant: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Li-Duan Tsai
  • Patent number: 8525328
    Abstract: The disclosure relates to a power device package structure. By employing the metal substrate of the power device package structure serve as a bottom electrode of a capacitor, the capacitor is integrated into the power device package structure. A dielectric material layer and a upper metal layer sequentially disposed on the metal substrate.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: September 3, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Jiin-Shing Perng, Min-Lin Lee, Shinn-Juh Lai, Huey-Ru Chang