Abstract: An embedded capacitor core including a first set of capacitors, a second set of capacitors, and an inter-layer dielectric film between the first set of capacitors and the second set of capacitors. The first set of capacitors includes: a first conductive pattern comprising at least two conductive electrodes; a second conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the first conductive pattern; and a first dielectric film between the first conductive pattern and the second conductive pattern. The second set of capacitors includes: a third conductive pattern comprising at least two conductive electrodes; a fourth conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the third conductive pattern; and a second dielectric film between the third conductive pattern and the fourth conductive pattern.

Abstract: The disclosure provides a capacitor structure. A first dielectric layer is disposed over the first electrode layer. A second electrode layer is disposed over the first dielectric layer. At least one of the first electrode layer and the second electrode layer has a peak-valley like structure to create at least two different gap distances therebetween, thereby providing parallel combinations of at least two different capacitances.

Abstract: An embedded capacitor device within a circuit board having an integrated circuitry thereon is provided. The circuit board has a common coupling area under the integrated circuitry. The embedded capacitor device includes a first capacitor section providing at least one capacitor to a first terminal set of the integrated circuitry and a second capacitor section providing at least one capacitor to a second terminal set of the integrated circuitry. A portion of the first capacitor section is in the common coupling area and has its coupling to the first terminal set located in the common coupling area. Similarly, a portion of the second capacitor section is in the common coupling area and has its coupling to the second terminal set located in the common coupling area.

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

Abstract: A capacitor device may include a first electrode, a second electrode, a third electrode, a first dielectric layer, and a second dielectric layer. The first electrode may be coupled with a first terminal of the capacitor device. The second electrode is under the first electrode and may be coupled with a second terminal of the capacitor device. The second electrode may be electrically isolated from the first electrode. The third electrode is under the first electrode and the second electrode and may be electrically isolated from the second electrode and electrically coupled with the first electrode. The first dielectric layer has a first dielectric constant and may be sandwiched between the first electrode and the second electrode. The second dielectric layer may have a second dielectric constant and may be sandwiched between the second electrode and the third electrode. In one embodiment, the second dielectric constant is at least five times larger than the first dielectric constant.

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract: A plurality of coaxial leads is made within a single via in a circuit substrate to enhance the density of vertical interconnection so as to match the demand for higher density multi-layers circuit interconnection between top circuit layer and bottom circuit layer of the substrate. Coaxial leads provide electromagnetic interference shielding among the plurality of coaxial leads in a single via.

Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via.

Abstract: A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals. At least one test pad is provided on the top surface of the multi-layered circuit board and each of the test pads is electrically connected to one of the multiple terminals. Then, detection occurs regarding one of the signal pads and one of the test pads that are electrically connected to a same one of the multiple terminals in order to determine a connection status of an electric path extending from the one signal pad through the same one terminal to the one test pad.

Abstract: An ESD protection substrate is disclosed. The ESD protection substrate includes a first conductor, a second conductor, a pointed structure, and an ESD protection material. The pointed structure is electrically connected to the first or the second conductor. The ESD protection material is disposed between the first and the second conductors.

Abstract: A capacitor device is provided. The capacitor device includes at least one capacitor. The capacitor device also includes a first capacitor and a first filter coupling the first capacitor and a conductive region, wherein the first capacitor has a first resonance frequency and the first filter is configured to operate at a first frequency band covering the first resonance frequency.

Abstract: A capacitive device is provided. The capacitive device includes a first electrode and a second electrode below the first electrode and spaced apart from the first electrode, wherein at least one of the first electrode and the second electrode includes a plurality of conductive step sections, the plurality of conductive step sections having different heights. The capacitive device also includes an insulating region between the first electrode and the second electrode; and at least one slot formed on one of the first electrode and the second electrode.

Abstract: A capacitive module is provided. The capacitive module may include a first capacitor including a first electrode and a second electrode, one of the first electrode and the second electrode being coupled to at least one first conductive via and the other one of the first electrode and the second electrode being coupled to at least one second conductive via. The capacitive module may also include a second capacitor spaced apart from the first capacitor, the second capacitor including a third electrode and a fourth electrode, one of the third electrode and the fourth electrode being coupled to the at least one first conductive via and the other one of the third electrode and the fourth electrode being coupled to the at least one second conductive via.

Abstract: An artificial retina chip module including a signal processing chip, a first polymer bump layer, and a photodiode array chip is provided. The signal processing chip includes a plurality of first pad disposed on a surface thereof. The first polymer bump layer includes a plurality of polymer bumps insulated from one another. Each of the first polymer bumps is composed of a polymer material and a conductive layer coated on the polymer material. Each first polymer bump is embedded into the corresponding first pad and the signal processing chip, wherein one end of the first polymer bump protrudes from the first pad and the other end thereof protrudes from a back surface of the signal processing chip. The photodiode array chip is disposed at one side of the signal processing chip and is electrically connected to the signal processing chip through the first polymer bumps.

Abstract: An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.

Abstract: A stepwise capacitor structure includes at least one stepwise conductive layer. The stepwise capacitor represents a feature of multiple capacitors. When currents flow through the stepwise capacitor, different current paths are presented in between an upper conductor and a bottom conductor of the stepwise capacitor in response to different current frequency; different inductor is induced in each path and decoupled by a stepwise capacitor structure as disclosed herein.

Abstract: A hybrid capacitor is provided which includes a substrate, at least one plate capacitor and at least one through hole capacitor. The substrate has through holes and the plate capacitors are on the substrate. At least one through hole capacitor and at least one plate capacitor are in parallel. The through hole capacitor at least includes an anode layer, a first dielectric layer, a first cathode layer and a second cathode layer. The anode layer is disposed on an inner surface of at least one through hole, and a surface of the anode layer is a porous structure. The first dielectric layer is disposed on the porous structure of the anode layer and covered with the first cathode layer. The first cathode layer is covered with the second cathode layer. A conductivity of the second cathode layer is larger than a conductivity of the first cathode layer.

Abstract: A hybrid capacitor is provided which includes a substrate, at least one plate capacitor and at least one through hole capacitor. The substrate has through holes and the plate capacitors are on the substrate. At least one through hole capacitor and at least one plate capacitor are in parallel. The through hole capacitor at least includes an anode layer, a first dielectric layer, a first cathode layer and a second cathode layer. The anode layer is disposed on an inner surface of at least one through hole, and a surface of the anode layer is a porous structure. The first dielectric layer is disposed on the porous structure of the anode layer and covered with the first cathode layer. The first cathode layer is covered with the second cathode layer. A conductivity of the second cathode layer is larger than a conductivity of the first cathode layer.