Patents by Inventor Min-Lin Lee

Min-Lin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8488299
    Abstract: The disclosure provides a capacitor structure. A first dielectric layer is disposed over the first electrode layer. A second electrode layer is disposed over the first dielectric layer. At least one of the first electrode layer and the second electrode layer has a peak-valley like structure to create at least two different gap distances therebetween, thereby providing parallel combinations of at least two different capacitances.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: July 16, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Shih-Hsien Wu, Min-Lin Lee, Shinn-Juh Lai, Shur-Fen Liu, Meng-Hua Chen, Chin-Hsien Hung
  • Patent number: 8304666
    Abstract: A plurality of coaxial leads is made within a single via in a circuit substrate to enhance the density of vertical interconnection so as to match the demand for higher density multi-layers circuit interconnection between top circuit layer and bottom circuit layer of the substrate. Coaxial leads provide electromagnetic interference shielding among the plurality of coaxial leads in a single via.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: November 6, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Ta Ko, Min-Lin Lee, Wei-Chung Lo, Shur-Fen Liu, Jinn-Shing King, Shinn-Juh Lai, Yu-Hua Chen
  • Patent number: 8289679
    Abstract: A decoupling device includes a lead frame, a capacitor unit, a metal layer, and a high dielectric organic-inorganic composite material layer. The lead frame includes a cathode terminal portion and an anode terminal portion. The capacitor unit is disposed on the lead frame. The capacitor unit includes a cathode portion, an anode portion, and an insulation portion located between the cathode portion and the anode portion. The cathode portion is electrically connected to the cathode terminal portion, and the anode portion is electrically connected to the anode terminal portion. The high dielectric organic-inorganic composite material layer is connected to the capacitor unit in parallel via the metal layer.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: October 16, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Liang Cheng, Chi-Lun Chen, Li-Duan Tsai, Min-Lin Lee, Shur-Fen Liu
  • Patent number: 8237520
    Abstract: A capacitor device is provided. The capacitor device includes at least one capacitor. The capacitor device also includes a first capacitor and a first filter coupling the first capacitor and a conductive region, wherein the first capacitor has a first resonance frequency and the first filter is configured to operate at a first frequency band covering the first resonance frequency.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 7, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Huey-Ru Chang, Min-Lin Lee, Jiin-Shing Perng, Sheng-Che Hung, Shinn-Juh Lai
  • Patent number: 8227894
    Abstract: A stepwise capacitor structure includes at least one stepwise conductive layer. The stepwise capacitor represents a feature of multiple capacitors. When currents flow through the stepwise capacitor, different current paths are presented in between an upper conductor and a bottom conductor of the stepwise capacitor in response to different current frequency; different inductor is induced in each path and decoupled by a stepwise capacitor structure as disclosed herein.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: July 24, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Min-Lin Lee, Shih-Hsien Wu, Shinn-Juh Lai, Shur-Fen Liu
  • Publication number: 20120168839
    Abstract: The disclosure relates to a power device package structure. By employing the metal substrate of the power device package structure serve as a bottom electrode of a capacitor, the capacitor is integrated into the power device package structure. A dielectric material layer and a upper metal layer sequentially disposed on the metal substrate.
    Type: Application
    Filed: July 14, 2011
    Publication date: July 5, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jiin-Shing Perng, Min-Lin Lee, Shinn-Juh Lai, Huey-Ru Chang
  • Publication number: 20120168217
    Abstract: An embedded capacitor substrate module includes a substrate, a metal substrate and a solid electrolytic capacitor material. The solid electrolytic capacitor material is formed on the metal substrate, so as to form a solid electrolytic capacitor with the substrate. The embedded capacitor substrate module further includes an electrode lead-out region formed by extending the substrate and the metal substrate. The metal substrate serves as a first electrode, and the substrate serves as a second electrode. An insulating material is formed between the substrate and the metal substrate. Therefore, the embedded capacitor substrate module is not only advantageous in having a large capacitance as the conventional solid capacitor, but also capable of being drilled or plated and electrically connected to other circuits after being embedded in a printed circuit board.
    Type: Application
    Filed: August 3, 2011
    Publication date: July 5, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chien-Min Hsu, Min-Lin Lee, Cheng-Liang Cheng, Li-Duan Tsai
  • Patent number: 8198538
    Abstract: A capacitive device is provided. The capacitive device includes a first electrode and a second electrode below the first electrode and spaced apart from the first electrode, wherein at least one of the first electrode and the second electrode includes a plurality of conductive step sections, the plurality of conductive step sections having different heights. The capacitive device also includes an insulating region between the first electrode and the second electrode; and at least one slot formed on one of the first electrode and the second electrode.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: June 12, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Shinn-Juh Lai, Huey-Ru Chang, Ray-Fong Hong
  • Patent number: 8179695
    Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: May 15, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Uei-Ming Jow, Chin-Sun Shyu, Chang-Sheng Chen, Min-Lin Lee, Shinn-Juh Lai
  • Patent number: 8174840
    Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: May 8, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Uei-Ming Jow, Chang-Sheng Chen, Chin-Sun Shyu, Min-Lin Lee, Shinn-Juh Lay, Ying-Jiunn Lai
  • Patent number: 8125761
    Abstract: A capacitive module is provided. The capacitive module may include a first capacitor including a first electrode and a second electrode, one of the first electrode and the second electrode being coupled to at least one first conductive via and the other one of the first electrode and the second electrode being coupled to at least one second conductive via. The capacitive module may also include a second capacitor spaced apart from the first capacitor, the second capacitor including a third electrode and a fourth electrode, one of the third electrode and the fourth electrode being coupled to the at least one first conductive via and the other one of the third electrode and the fourth electrode being coupled to the at least one second conductive via.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: February 28, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Shinn-Juh Lai, Chen-Hsuan Chiu
  • Patent number: 8094429
    Abstract: A capacitor device may include a first electrode, a second electrode, a third electrode, a first dielectric layer, and a second dielectric layer. The first electrode may be coupled with a first terminal of the capacitor device. The second electrode is under the first electrode and may be coupled with a second terminal of the capacitor device. The second electrode may be electrically isolated from the first electrode. The third electrode is under the first electrode and the second electrode and may be electrically isolated from the second electrode and electrically coupled with the first electrode. The first dielectric layer has a first dielectric constant and may be sandwiched between the first electrode and the second electrode. The second dielectric layer may have a second dielectric constant and may be sandwiched between the second electrode and the third electrode. In one embodiment, the second dielectric constant is at least five times larger than the first dielectric constant.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: January 10, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Shinn-Juh Lai
  • Patent number: 8071890
    Abstract: An electrically conductive structure includes a first conductive structure and a second conductive structure. Each has a conducting section at one end and a coupling section at the other end. The first and second conducting sections are electrically connected to a power and ground contact of an electronic device, respectively. The first and second coupling sections are respectively connected with power and ground layer of a circuit board. The first coupling sections are connected with the first conducting section through first extending sections and the second coupling sections are connected with the second conducting section through second extending sections. At least two coupling sections of the conductive structures are arranged in pairs. The first conductive structure and the second conductive structure are arranged in a staggered array to form two wiring loops having opposite current directions, thereby generating a magnetic flux cancellation effect.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: December 6, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Shih-Hsien Wu, Shinn-Juh Lai, Min-Lin Lee
  • Patent number: 8049512
    Abstract: A circuit board with embedded components includes a plurality of embedded components and at least one transmission line electrically connected to at least one of the embedded components and having a terminal circuit. Therefore, a measuring device is used to be electrically connected to the transmission line and send out a signal, so as to receive a corresponding reflected signal, and then, compare the received reflected signal with a signal pattern in the database to obtain an electrical parameter of the embedded component.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: November 1, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Uei-Ming Jow, Min-Lin Lee, Shinn-Juh Lai, Chin-Sun Shyu, Chang-Sheng Chen, Ying-Jiunn Lai
  • Patent number: 8035951
    Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: October 11, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Shih-Hsien Wu, Shinn-Juh Lai, Min-Lin Lee, Shur-Fen Liu
  • Patent number: 8035036
    Abstract: A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: October 11, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Uei-Ming Jow, Min-Lin Lee, Shinn-Juh Lay, Chin-Sun Shyu, Chang-Sheng Chen, Ying-Jiunn Lai
  • Patent number: 8026603
    Abstract: An interconnect structure of an integrated circuit and manufacturing method therefore are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: September 27, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Yu Hsu, Chih-Yuan Cheng, Shyi-Ching Liau, Min-Lin Lee, Ra-Min Tain, Rong-Chang Feng
  • Publication number: 20110157775
    Abstract: A decoupling device includes a lead frame, a capacitor unit, a metal layer, and a high dielectric organic-inorganic composite material layer. The lead frame includes a cathode terminal portion and an anode terminal portion. The capacitor unit is disposed on the lead frame. The capacitor unit includes a cathode portion, an anode portion, and an insulation portion located between the cathode portion and the anode portion. The cathode portion is electrically connected to the cathode terminal portion, and the anode portion is electrically connected to the anode terminal portion. The high dielectric organic-inorganic composite material layer is connected to the capacitor unit in parallel via the metal layer.
    Type: Application
    Filed: May 10, 2010
    Publication date: June 30, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Cheng-Liang Cheng, Chi-Lun Chen, Li-Duan Tsai, Min-Lin Lee, Shur-Fen Liu
  • Patent number: 7894178
    Abstract: A through hole capacitor at least including a substrate, an anode layer, a dielectric layer, a first cathode layer, and a second cathode layer is provided. The substrate has a plurality of through holes. The anode layer is disposed on the inner surface of at least one through hole, and the surface of the anode layer is a porous structure. The dielectric layer is disposed on the porous structure of the anode layer. The first cathode layer covers a surface of the dielectric layer. The second cathode layer covers a surface of the first cathode layer, and the conductivity of the second cathode layer is greater than that of the first cathode layer. The through hole capacitor can be used for impedance control, as the cathode layers of the through hole are used for signal transmission.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: February 22, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Bang-Hao Wu, Li-Duan Tsai, Min-Lin Lee, Cheng-Liang Cheng
  • Patent number: 7894172
    Abstract: An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: February 22, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chi-Liang Pan, Min-Lin Lee, Shinn-Juh Lai, Shih-Hsien Wu, Chen-Hsuan Chiu