Abstract: A method and apparatus for dosage measurement and monitoring in an ion implantation system is disclosed. In one embodiment, a transferring system, includes: a vacuum chamber, wherein the vacuum chamber is coupled to a processing chamber; a shaft coupled to a ball screw, wherein the ball screw and the shaft are configured in the vacuum chamber; and a vacuum rotary feedthrough, wherein the vacuum rotary feedthrough comprises a magnetic fluid seal so as to provide a high vacuum sealing, and wherein the vacuum rotary feedthrough is configured through a first end of the vacuum chamber and coupled to the ball screw so as to provide a rotary motion on the ball screw.

Abstract: A method of fabricating a sensing apparatus is disclosed. The method includes providing a substrate that includes a plurality of image sensors, forming an optical filtering film on the substrate, and forming a collimator on the optical filtering film. The method further includes forming a blocking layer on the collimator and forming an illumination layer on the blocking layer. The illumination layer is configured to illuminate an object placed above the illumination layer. The image sensors are configured to detect a portion of light reflected from the object.

Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

Abstract: A showering appliance includes a handheld showerhead and a fixed shower head which includes a fixed portion, a first outlet portion, a first peripheral portion, and a first connector. The fixed portion has a first inlet channel communicating with the first outlet portion. The first peripheral portion is located around the first outlet portion and is disposed with the first connector. The handheld showerhead includes a handle, a second outlet portion, a second peripheral portion, and a second connector. The handle has a second inlet channel communicating with the second outlet portion. The second peripheral portion is located around the second outlet portion and is disposed with the second connector. The first connector and the second connector are magnetically attracted to each other, so that the handheld shower head could be magnetically attached to the first peripheral portion of the fixed shower head, thereby fixing the handheld showerhead.

Abstract: The present invention relates generally to a multifunctional textile produced by a special processing method and the manufacturing method and use thereof. The water repellent agent and flame retardant incompatible with each other are laminated by using special materials and a specific processing method to form a multifunctional textile with special water repellency, soil repellency, oil repellency, mildew resistance and flame retardancy, which comprises a base cloth layer, two composite layers and a flame retardant layer. The base cloth layer has a first surface and a second surface opposite to the first surface, the two composite layers are disposed on the first surface and the second surface respectively, and then the flame retardant layer is disposed on the composite layer of the first surface of the base cloth layer.

Abstract: A memory storage apparatus including a memory array and a controller circuit is provided. The memory array is configured to store a first error correcting code and a first data. The controller circuit is coupled to the memory array. The controller circuit is configured to read the first data from the memory array and determine whether an error bit of the first data is one of one or more data mask bits to decide whether to update the first error correcting code stored in the memory array. The controller circuit includes a switch element. The switch element is coupled to the memory array. The switch element receives the first data from the memory array. An error correcting procedure is not performed on the first data. In addition, a data access method is also provided.

Abstract: A level shifter includes a self-initialization circuit. The self-initialization circuit judges whether the input signal and the inverted input signal received by the level shifter are invalid while a power supply voltage is powered up. If the self-initialization circuit confirms that the input signal and the inverted input signal received by the level shifter are invalid, the self-initialization circuit controls the level shifter to be maintained in a self-initializing power up state. Consequently, the output signal from the level shifter has the specified voltage level.

Abstract: Systems and methods are provided for use in a Simple Network Management Protocol (“SNMP”) computing environment, by which efficiency of computing systems employing SNMP may be improved. An SNMP message is parsed, and the parsed information used to construct a binary tree. By using a binary tree, which is a data object that consumes less memory resources, efficiency of interactions between elements of the SNMP computing environment are improved. A method can include receiving a SNMP request for data. Then, the SNMP request is parsed and a binary tree constructed from the parsed SNMP request. The binary tree includes a plurality of type-length-value nodes. The length value of each non-leaf node is the summation of the length values of all the child nodes below the non-leaf node; and the length value of each leaf node is the length of the data requested.

Abstract: A counting device, including multiple counting circuit stages and a first logic operation circuit, is provided. The counting circuit stages are serially coupled in sequence. A first counting circuit stage performs a counting action according to a first clock signal and generates a first counting result. Second to Nth counting circuit stages perform counting actions according to a second clock signal, where N is a positive integer greater than 2. The first logic operation circuit provides the first counting result to be the second clock signal according to an indication signal.

Abstract: A vehicular head-up display system provides a driver with two virtual images in different image distances, wherein each of the virtual images utilizes all pixels of a single image source. Linearly polarized light beams, which are emanated from the image source, pass through a dynamic polarization converter, whereby to form two image light beams with orthogonal polarization states that are switched fast for time-multiplexing. The two image light beams are selected by a polarization selection component for transmission and reflection respectively. The reflected image light beam is handled by an optical relay component to form an intermediate image. A curved mirror reflects the two image light beams to a virtual image reflecting surface to form two virtual images in different virtual image distances in respect to eyes of a driver in front of the virtual image reflecting surface.

Abstract: A power amplifier (PA) linearization technique with a wider linearized power range is proposed. Proposed two types of linearizers with cross-coupled PMOS and NMOS configuration. The idea is to use a complimentary device compared with the PA core device, and the behavior of Cgs of the linearizer are also complimentary to the PA itself. In the other words, the overall Cgs of the PA with the linearizer would be constant without leading to non-linear waveform. Both linearizers can effectively compensate not only AMAM but also AMPM. First type of linearizer can be integrated with PA cores, and second type of linearizer can be used in the IMN. Both linearizers have effective IM3 reduction in different corner.

Abstract: A piezoelectric motorization system has a mechanically flexible body that has one or more surfaces for placing piezoelectric actuators. The system has groups of piezoelectric actuators each positioned on one of the surfaces of the mechanically flexible body that is connected to the electronic circuitry. The electronic circuitry controls the driving of the mechanical loads by the mechanically flexible body by injecting sets of control signals into different groups of actuators positioned on the mechanically flexible body. Each control signal operates groups of driving frequencies with an adjustable amplitude ratio and an adjustable phase difference among driving frequencies. And, under a set of boundary conditions exhibited by a set of structural dimensions of the mechanically flexible body, each control signal induces multi-mode resonance of the mechanically flexible body for driving the mechanical loads multi-dimensionally.

Abstract: A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.

Abstract: An insulator for an ion implantation source may provide electrical insulation between high voltage components and relatively lower voltage components of the ion implantation source. To reduce the likelihood of and/or prevent a leakage path forming along the insulator, the insulator may include an internal cavity having a back and forth pattern. The back and forth pattern of the internal cavity increases the mean free path of gas molecules in the ion implantation source and increases the surface area of the insulator that is not directly or outwardly exposed to the gas molecules. This results in a continuous film or coating being more difficult and/or less likely to form along the insulator, which extends the working time of the ion implantation source.

Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.

Abstract: A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.

Abstract: A level shifter includes a self-initialization circuit. The self-initialization circuit judges whether the input signal and the inverted input signal received by the level shifter are invalid while a power supply voltage is powered up. If the self-initialization circuit confirms that the input signal and the inverted input signal received by the level shifter are invalid, the self-initialization circuit controls the level shifter to be maintained in a self-initializing power up state. Consequently, the output signal from the level shifter has the specified voltage level.

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

Abstract: The present invention discloses a method for preparing a fiber with spatial structure, and the fiber prepared thereby and its use as well. In this method, the fiber is prepared through a wet spinning process, wherein a spinning solution prepared from low molecular weight polysaccharide based polyelectrolyte optionally with inert conductive material distributed therein, is injected through a syringe into a coagulation bath, which is formed by adding high molecular weight polysaccharide based polyelectrolyte into a coagulation tank. This method has the advantages such as simple equipment, low cost, good spinnability, and is applicable for large-scale production. The prepared fiber with spatial structure, especially the hollow multilayered fiber, has the controllable layers, cavities, and diameter, a high tensile strength, and an ultra-high specific surface area.