Abstract: A semiconductor device includes a slew rate controller configured to receive a mode register set signal and data and to activate a driving strength control signal for controlling the driving strength of a driving unit using the data in response to a code value of the mode register set signal. The driving unit is configured to pull a data output terminal up and down in response to the driving strength control signal.

Abstract: Disclosed herein is an apparatus for collecting game data in order to test performance of a game server. The apparatus includes a capture and filtering module, a control module, and a data management module. The capture and filtering module captures packets, transmitted and received between the game server and each of a plurality of game clients, using the plurality of game clients, and extracts a plurality of necessary data by performing filtering on the results of the capturing. The control module determines the movement route of a game character in such a way as to correspond to the plurality of necessary data, and controls the plurality of game clients based on the movement route. The data management module stores and manages the plurality of necessary data.

Abstract: Disclosed herein is a scenario-based load testing apparatus and method. The scenario-based load testing apparatus includes a packet analysis unit, a scenario creation unit, and a load generation unit. The packet analysis unit creates a virtual map and game grammar by capturing and analyzing packets sent between a server and a client. The scenario creation unit creates a scenario of a virtual user on the virtual map. The load generation unit generates a load by creating packet data corresponding to the virtual user in compliance with the game grammar and the scenario.

Abstract: A semiconductor device includes a slew rate controller configured to receive a mode register set signal and data and to activate a driving strength control signal for controlling the driving strength of a driving unit using the data in response to a code value of the mode register set signal. The driving unit is configured to pull a data output terminal up and down in response to the driving strength control signal.

Abstract: A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, sequentially activates the data and a first pull-up delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-up delayed signals having different delay times in the second mode of operation. A pull-up driving unit sequentially pulls a data output terminal up in response to the data and the first to third pull-up delayed signals.

Abstract: Provided is an apparatus for a parser framework having the characteristics of the application program, using the markup language.

Abstract: The present invention relates to a technology for easily generating and supplying a virtual client managing module specified for various games and testing the load and function of a game through a virtual client managing module and an apparatus for managing a virtual client. The device for managing a virtual client managing module according to the exemplary embodiment of the present invention performs a function that uses template specialized for each type of game as game unique information to generate a specialized module and generates the virtual client managing module combined with the common module. The apparatus for managing the virtual client generates and controls the virtual client based on the virtual client managing module.

Abstract: Provided are an apparatus and method for analyzing a characteristic of a game player in real time. The apparatus includes at least one individual action determiner for calculating a player characteristic value indicating a level or tendency of a game player by giving a first weight to game play data values resulting from game play of the game player, an accuracy determiner for comparing the player characteristic value and a value set by an administrator, and calculating an accuracy value of the individual action determiner, a comprehensive level determiner for calculating a final characteristic value indicating a level or tendency of the game player by giving a second weight to the player characteristic values calculated by the individual action determiners when the accuracy value do not exceed a reference value, and a characteristic value output unit for outputting the final characteristic value.

Abstract: An apparatus for visualizing game packet data, includes a packet capturing unit for capturing game packet data transmitted and received during a game service; a decryption unit for decrypting the captured game packet data; and a packet filtering unit for extracting packet data having a valid protocol ID from the game packet data and extracting visualization data from the extracted packet data. Further, the apparatus for visualizing game packet data includes a virtual map creation unit for creating a virtual map using the extracted visualization data; and a visualization unit for displaying the visualization data in the created virtual map.

Abstract: A game grammar-based packet capture and analysis apparatus for conducting game test, includes: a packet capture unit for capturing packets of game data transmitted and received between a game client and a game server; a packet analysis unit for analyzing the packets captured by the packet capture unit to generate a game grammar based on analyzed results. Further, the game grammar-based packet capture and analysis apparatus includes a load generation unit for generating packets in compliance with the game grammar to apply the packets to the game server as a load.

Abstract: A semiconductor memory device having a redundancy memory block and a cell array structure thereof, the semiconductor memory device having a plurality of sub-mats constituting a memory cell array, wherein each of the plurality of sub-mats includes a plurality of normal memory blocks of which each includes a plurality of normal memory cells and that are disposed adjacent one another; and at least one redundancy memory block having the same structure as the plurality of normal memory blocks, being disposed adjacent at least one of the plurality of normal memory blocks and having a plurality of redundancy memory cells for a row and column repair, thereby enhancing a redundancy efficiency.

Abstract: An apparatus for adjusting difficulty level of a game, includes: an artificial intelligence unit for storing artificial intelligence algorithms; a strategy toolkit for generating metadata for game resources and creating game strategies by applying the artificial intelligence algorithms using the metadata; and a simulation toolkit for calculating relative difficulty levels of the game strategies and combinations of the game strategies and applying to the game one of the game strategies and the combinations of the game strategies based on a user's skill level determined during the game.

Abstract: A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, sequentially activates the data and a first pull-up delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-up delayed signals having different delay times in the second mode of operation. A pull-up driving unit sequentially pulls a data output terminal up in response to the data and the first to third pull-up delayed signals.

Abstract: A multithreading framework supporting dynamic load balancing, the multithreading framework being used to perform multi-thread programming, the multithreading framework includes a job scheduler for performing parallel processing by redefining a processing order of one or more unit jobs, transmitted from a predetermined application, based on unit job information included in the respective unit jobs, and transmitting the unit jobs to a thread pool based on the redefined processing order, a device enumerator for detecting a device in which the predetermined application is executed and defining resources used inside the application, a resource manager for managing the resources related to the predetermined application executed using the job scheduler or the device enumerator, and a plug-in manager for managing a plurality of modules which performs various types of functions related to the predetermined application in a plug-in manner, and providing such plug-in modules to the job scheduler.

Abstract: A semiconductor memory device which a pad for receiving a power voltage, a first power line connected to the pad, and a plurality of second power lines respectively connected to memory cells of a repair unit. A selection circuit outputs selection signals for selecting the memory cells of the array in the repair unit in response to a row address in a test operation mode. A power switch circuit operates in response to the selection signals, and connects the second power line connected to the selected memory cells with the first power line in the test operation mode. The power switch circuit disconnects the remaining second power lines from the first power line.

Abstract: A semiconductor memory device having a redundancy memory block and a cell array structure thereof, the semiconductor memory device having a plurality of sub-mats constituting a memory cell array, wherein each of the plurality of sub-mats includes a plurality of normal memory blocks of which each includes a plurality of normal memory cells and that are disposed adjacent one another; and at least one redundancy memory block having the same structure as the plurality of normal memory blocks, being disposed adjacent at least one of the plurality of normal memory blocks and having a plurality of redundancy memory cells for a row and column repair, thereby enhancing a redundancy efficiency.