Abstract: A battery pack includes a plurality of battery modules, each battery module including: a cell stack that includes a plurality of battery cells arranged in a first direction; and a side cover disposed on at least one side of the cell stack; and a pack housing structured to accommodate the plurality of battery modules, wherein the side cover includes a body disposed at a side of the cell stack in the first direction; a first extension portion extending from the body in the first direction; and a second extension portion connected to the body and the first extension portion.

Abstract: A display device, includes: a display area and a non-display area; a plurality of signal lines over the display area; and a plurality of connection lines in the display area and connected to the signal lines, wherein the plurality of connection lines includes a plurality of first connection lines connected to the signal lines, respectively, a plurality of third connection lines on a same layer as the first connection lines, and a plurality of second connection lines connecting the first connection lines to the third connection lines.

Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.

Abstract: Disclosed is a case for a battery module including a body having an internal space; and an end plate disposed on an end of the body, wherein the body includes a bottom plate on which a coolant flow path through which a coolant flows is formed, and wherein the end plate includes a coolant flow tube through which the coolant flows and a connection portion extending from the coolant flow tube and coupled to the coolant flow path.

Abstract: Integrated circuit devices may include a first upper channel region on a substrate, a first lower channel region between the substrate and the first upper channel region, a first intergate insulator that is between the first lower channel region and the first upper channel region and includes a lower portion and an upper portion, an upper gate electrode, and a lower gate electrode between the substrate and the upper gate electrode. The first upper channel region and the upper portion of the first intergate insulator may be in the upper gate electrode. The first lower channel region and the lower portion of the first intergate insulator are in the lower gate electrode.

Abstract: The present disclosure relates to an anode for a lithium secondary battery, wherein an anode material layer is formed on at least one surface of an anode current collector, and the anode material layer includes large-particle graphite, a small-particle silicon-based material, and fine-particle graphite, and satisfies the following conditions 1 to 3: [Condition 1] Average diameter D50 of the large-particle graphite (D1): 1 to 50 ?m [Condition 2] Average diameter D50 of the small-particle silicon-based material (D2): 0.155D1 to 0.414D1 [Condition 3] Average diameter D50 of the fine-particle graphite (D3): 0.155D1 to 0.414D1, or 0.155D2 to 0.414D2.

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a sacrificial layer in a preliminary substrate by adding an element into the preliminary substrate, forming a transistor structure on the preliminary substrate, the transistor structure including a source/drain region, replacing the sacrificial layer with a power contact that comprises an upper surface contacting the source/drain region, and forming a power rail that contacts a lower surface of the power contact.

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.

Abstract: A window replacement display device having a memory that stores landscape information, a clock unit that generates current time information, a display unit for displaying the landscape information, and a control unit configured to change the landscape information according to the current time information and to display it on the display unit.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

Abstract: In some embodiments, a semiconductor device includes a first active pattern extended in a first horizontal direction on a substrate, a second active pattern extended in the first horizontal direction on the substrate, a first bottom gate electrode extended in a second horizontal direction on the first active pattern, a first upper gate electrode extended in the second horizontal direction on the first bottom gate electrode, a second bottom gate electrode extended in the second horizontal direction on the second active pattern, a second upper gate electrode extended in the second horizontal direction on the second bottom gate electrode, and a first gate cut comprising a first portion isolating the first bottom gate electrode from the second bottom gate electrode and a second portion isolating the first upper gate electrode from the second upper gate electrode. A width of the second portion exceeds a width of the first portion.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises an insulating structure, a dielectric structure, a metal structure, a conductive spacer and a dielectric spacer. The dielectric structure is formed on the insulating structure. The metal structure is formed on and surrounded by the dielectric structure. A bottom surface and a lateral surface of the metal structure are in direct contact with the dielectric structure. The conductive spacer is formed on the insulating structure. The conductive spacer surrounds the dielectric structure. The dielectric spacer is formed on the insulating structure, wherein the dielectric spacer surrounds the conductive spacer.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a source region, a drain region, a gate region and a gate oxide. The gate region is disposed between the source region and the drain region. The gate oxide is disposed on the gate region. A bottom interface is between the gate region and the gate oxide, and an entire of the bottom interface is substantially flat.

Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

Abstract: The battery module according to the present disclosure comprises a plurality of battery cells stacked in one direction; a module case accommodating the plurality of battery cells; and a vent positioned on top of the plurality of battery cells, wherein the vent comprises a plurality of partitions forming a plurality of flow channels distinguished from each other.

Abstract: A battery module and a battery pack including the same are disclosed. In some implementations, the battery module may include a plurality of battery cells; and a cell monitoring portion connected to the plurality of battery cells, the cell monitoring portion including a plurality of boards collecting information on at least one of temperature, current, and voltage of the plurality of battery cells. The plurality of boards may be separable.

Abstract: Disclosed is a method for controlling a fuel cell of a fuel cell vehicle. The method comprises determining a reference output required for restarting or stopping power generation of a fuel cell according to a required output of a vehicle, correcting the reference output based on vehicle driving condition information comprising a vehicle altitude and coolant temperature and degree of degradation of the fuel cell, and restarting or stopping the power generation of the fuel cell based on the corrected reference output.

Abstract: A coil component includes a body, an internal insulating layer disposed in the body, and a coil portion disposed on the internal insulating layer. The coil portion includes first and second coil patterns disposed on opposing surfaces of the internal insulating layer, respectively, first main and first auxiliary lead-out portions extending from the first coil pattern and respectively exposed to a front surface and one side surface of the body connected to each other, and second main and second auxiliary lead-out portions extending from the second coil pattern and respectively exposed to a rear surface and another side surface of the body connected to each other.

Abstract: A display device, includes: a display area and a non-display area; a plurality of signal lines over the display area; and a plurality of connection lines in the display area and connected to the signal lines, wherein the plurality of connection lines includes a plurality of first connection lines connected to the signal lines, respectively, a plurality of third connection lines on a same layer as the first connection lines, and a plurality of second connection lines connecting the first connection lines to the third connection lines.