Abstract: A display device includes: a display panel including a bending area; and a first passivation film and a second passivation film disposed on a first surface of the display panel to be spaced apart from each other. The second passivation film includes a first flat portion and a first stepped portion overlapping the bending area, and a thickness of the first stepped portion is less than a thickness of the first flat portion.

Abstract: Interlayer dielectric (ILD) layer(s) of a semiconductor device may be configured as a gate oxide for high-voltage transistors, and therefore additional process operations to deposit dedicated gate oxide layers are not needed. Moreover, additional processing operations to form the gate structures of the high-voltage fin-based PMOS transistors and high-voltage fin-based NMOS transistors are not needed in that middle end of line (MEOL process and back end of line (BEOL) processes can be used as the gate formation process of the high-voltage transistors.

Abstract: A semiconductor device includes a substrate, a lower active pattern which is spaced apart from the substrate and extends in a first direction, an upper active pattern on the lower active pattern, the upper active pattern being spaced apart from the lower active pattern and extending in the first direction, a gate structure on the substrate, the gate structure extending in a second direction intersecting the first direction, and a cutting pattern on the substrate, the cutting pattern extending in the first direction to cut the gate structure. The gate structure includes a lower gate electrode through which the lower active pattern penetrates, an upper gate electrode which is connected to the lower gate electrode and through which the upper active pattern penetrates, and an insulating pattern on one side of the cutting pattern, the insulating pattern being arranged with the upper gate electrode along the second direction.

Abstract: A method of predicting a battery lifespan includes estimating a state of health (SOH) of a battery by integrating an amount of electric current while a state of charge (SOC) of the battery mounted in each of a plurality of systems changes, dividing the plurality of systems into a plurality of groups according to a usage pattern collected by each of the plurality of systems at every predetermined period, generating a usage scenario of the battery in each of the plurality of systems, using a usage environment of each of the plurality of groups and the usage pattern, and predicting, for each of the plurality of systems, an end-of-life time of the battery using the usage scenario and the SOH of the battery.

Abstract: A semiconductor structure includes a substrate, a first FET device and a second FET device. The substrate has a first region and a second region. The first FET device is in the first region, and the second FET device is in the second region. The first FET device includes a first isolation structure, a first gate electrode disposed over a portion of the first isolation structure, and a first gate dielectric layer between the substrate and the first gate electrode. The first gate dielectric layer has a first thickness. The second FET device includes a plurality of fin structures, a plurality of second isolation structures, a second gate electrode over the plurality of fin structures, and a second gate dielectric layer between the second gate electrode and the plurality of fin structures. The second gate dielectric layer has a second thickness. The second thickness is less than the first thickness.

Abstract: A method for detecting an abnormal fault of a battery, includes measuring cell data from battery cells included in a battery pack for a predetermined period of time; generating two-dimensional input data by mapping the cell data on a two-dimensional plane having a first axis corresponding to the period of time and a second axis corresponding to an index of each of the battery cells; inputting the two-dimensional input data into an abnormal fault detection model pre-trained to detect the abnormal fault in the battery; and determining whether an abnormal cell, having entered an abnormal state, among the battery cells, is present, based on an output of the abnormal fault detection model.

Abstract: Disclosed is a vehicle system including: a first electronic device configured to receive a radio frequency (RF) signal from an external device and process the RF signal to generate data; and a second electronic device configured to receive the data through an Ethernet communication method and perform an operation based on the data, wherein the first electronic device includes: a first signal detector configured to receive a first wake-up signal in a power saving mode state; and a first Ethernet interface configured to attempt an Ethernet connection with the second electronic device when the first signal detector receives the first wakeup signal.

Abstract: A semiconductor device includes a substrate extending a first direction and a second direction perpendicular to the first direction, an active pattern that protrudes from the substrate in a third direction perpendicular to the first direction and the second direction, a first plurality of lower nanosheets, a second plurality of lower nanosheets stacked spaced apart from the first plurality of lower nanosheets in the first direction, a first plurality of upper nanosheets spaced apart from the first plurality of lower nanosheets in the third direction, and a second plurality of upper nanosheets spaced apart from the second plurality of lower nanosheets in the third direction. A first upper gate electrode surrounding the first plurality of upper nanosheets. A second upper gate electrode surrounding the second plurality of upper nanosheets. A width of the first plurality of upper nanosheets is different from a width of the second plurality of upper nanosheets.

Abstract: Disclosed is a clothes treating apparatus and a control method thereof. Specifically, the clothes treating apparatus may include an inverter configured to convert a direct current (DC) input into an alternating current (AC) output and provide the AC output to the motor, and a controller configured to control the inverter in relation to driving of the motor.

Abstract: A semiconductor device includes a substrate, an active pattern on the substrate, a plurality of lower nanosheets stacked on the active pattern, a separation structure spaced apart from the plurality of lower nanosheets in the vertical direction and disposed on the plurality of lower nanosheets, and including first to third layers sequentially stacked on each other, a plurality of upper nanosheets spaced apart from the separation structure in the vertical direction and disposed on the separation structure, and stacked on the separation structure, and a gate electrode extending in a second horizontal direction different from the first horizontal direction, and surrounding the separation structure, each of the plurality of lower nanosheets, and each of the plurality of upper nanosheets. The first and third layers include the same material, and each of the first layer and the third layer includes a material different from a material of the second layer.

Abstract: A secondary battery includes an electrode assembly, and a battery case accommodating the battery case together with an electrolytic solution. The battery case includes a metal. The battery case is opened in its upper part; and a cap assembly that is coupled to the opened upper part of the can body. The can body includes a beading part that is bent inward at the upper part of the housing part, and a crimping part that is bent in a direction in which the cap assembly is located at an upper part of the beading part. At least one of the bottom part or the crimping part of the can body has a metal member inserted therein. The metal member has a lower melting point than the metal of the can body.

Abstract: Disclosed is a motor control apparatus, a motor control system, and a motor control method that estimate a stator resistance and a rotor position for sensorless control of a motor.

Abstract: A semiconductor device is provided. The semiconductor device includes a first die, a second die, a first through via, and a second through. The first die includes a first substrate, a first interconnection structure disposed on the first substrate, and a plurality of first bonding substructures over the first interconnect structure. The second die includes a second substrate, a second interconnect structure disposed on the second substrate, and a plurality of second bonding substructures over the second interconnect structure. The plurality of second bonding substructures are bonded to the plurality of first bonding substructures. The first through via and the second through via extend through the second substrate and to the second interconnect structure, wherein the first through via and the second through via are electrically disconnected to each other.

Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a region. A first gate structure and a sacrificial gate structure are recessed in the substrate and disposed in the region. The sacrificial gate structure is adjacent to the first gate structure. A first contact is electrically connected to the first gate structure. A sacrificial gate masking structure is disposed over the sacrificial gate structure. An upper surface of the sacrificial gate structure is entirely covered by the sacrificial gate masking structure.

Abstract: A display device includes: a display panel including a bending area; and a first passivation film and a second passivation film disposed on a first surface of the display panel to be spaced apart from each other. The second passivation film includes a first flat portion and a first stepped portion overlapping the bending area, and a thickness of the first stepped portion is less than a thickness of the first flat portion.

Abstract: A semiconductor structure includes a first device, a second device, and a plurality of pillars. The first device includes a first dielectric layer, a first high-k dielectric layer over the first dielectric layer, and a first metal gate structure. The second device includes a second dielectric layer, a second high-k dielectric layer over the second dielectric layer, and a second metal gate structure. The first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the second thickness is less than the first thickness. The pillars are disposed in the first metal gate structure. The pillars are separated from each other by the first metal gate structure.

Abstract: A battery module includes a battery cell stack in which a plurality of battery cells are stacked, a first frame member accommodating the battery cell stack and having an open upper portion, a second frame member covering the battery cell stack from an upper portion of the first frame member, a connection portion coupling the first frame member and the second frame member to each other, and an insulating sheet disposed between the battery cell stack and the second frame member, wherein the insulating sheet is disposed to extend up to a region in which the connection portion is positioned.

Abstract: Embodiments of the present disclosure include an optical/electrical hybrid male connector, a female connector, and an optical/electrical hybrid connector system. The optical/electrical hybrid male connector includes a male base and at least two optical connectors. The male base includes a base body and at least two male accommodating channels disposed on the base body. The at least two male accommodating channels one-to-one correspond to the at least two optical connectors, and each optical connector is mounted on one corresponding male accommodating channel.

Abstract: A battery module includes a plurality of battery cells stacked in one direction; and an end plate assembly covering an outermost battery cell disposed on the outermost among the plurality of battery cells, wherein the end plate assembly includes at least one thermistor for measuring a temperature of the outermost battery cell.

Abstract: Provided in the present invention are an optimization method and system for a medical system, and a computer-readable storage medium. The method comprises: setting a plurality of virtual examination targets and a plurality of virtual nodes, wherein the plurality of virtual nodes separately have an initial quantity of virtual resources; controlling the plurality of virtual examination targets to sequentially pass through the plurality of virtual nodes to simulate a plurality of actual examination phases in a medical examination procedure; and in the process of simulation, determining a node to be optimized in the plurality of virtual nodes based on a current simulation result, and adjusting the quantity of virtual resources of the node to be optimized.