Abstract: A semiconductor structure includes a first device, a second device, and a plurality of pillars. The first device includes a first dielectric layer, a first high-k dielectric layer over the first dielectric layer, and a first metal gate structure. The second device includes a second dielectric layer, a second high-k dielectric layer over the second dielectric layer, and a second metal gate structure. The first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the second thickness is less than the first thickness. The pillars are disposed in the first metal gate structure. The pillars are separated from each other by the first metal gate structure.

Abstract: A battery module includes a battery cell stack in which a plurality of battery cells are stacked, a first frame member accommodating the battery cell stack and having an open upper portion, a second frame member covering the battery cell stack from an upper portion of the first frame member, a connection portion coupling the first frame member and the second frame member to each other, and an insulating sheet disposed between the battery cell stack and the second frame member, wherein the insulating sheet is disposed to extend up to a region in which the connection portion is positioned.

Abstract: A battery module includes a plurality of battery cells stacked in one direction; and an end plate assembly covering an outermost battery cell disposed on the outermost among the plurality of battery cells, wherein the end plate assembly includes at least one thermistor for measuring a temperature of the outermost battery cell.

Abstract: Embodiments of the present disclosure include an optical/electrical hybrid male connector, a female connector, and an optical/electrical hybrid connector system. The optical/electrical hybrid male connector includes a male base and at least two optical connectors. The male base includes a base body and at least two male accommodating channels disposed on the base body. The at least two male accommodating channels one-to-one correspond to the at least two optical connectors, and each optical connector is mounted on one corresponding male accommodating channel.

Abstract: Provided in the present invention are an optimization method and system for a medical system, and a computer-readable storage medium. The method comprises: setting a plurality of virtual examination targets and a plurality of virtual nodes, wherein the plurality of virtual nodes separately have an initial quantity of virtual resources; controlling the plurality of virtual examination targets to sequentially pass through the plurality of virtual nodes to simulate a plurality of actual examination phases in a medical examination procedure; and in the process of simulation, determining a node to be optimized in the plurality of virtual nodes based on a current simulation result, and adjusting the quantity of virtual resources of the node to be optimized.

Abstract: A display device may include a display panel including a display area, a non-display area which may be disposed on a periphery of the display area, and a pad area which may be disposed on one side of the non-display area. The display panel may include data lines disposed in the display area of the display panel along a second direction which intersects a first direction, and connection lines disposed in the display area of the display panel along the first direction. A first data line among the data lines may be connected to a first connection line among the connection lines.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a substrate; a gate electrode disposed within the substrate; a gate dielectric layer disposed within the substrate and surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure disposed over the gate dielectric layer and contacting the gate dielectric layer; and a pair of source/drain regions on opposing sides of the gate dielectric layer.

Abstract: Disclosed is a motor control apparatus including an inverter part configured to convert DC power into AC power and provide the AC power to a motor, and a controller configured to control driving of the motor by using the inverter part, the controller configured to identify a stop position of a rotor in previous driving of the motor, and control the inverter part to apply an input signal of a specific pattern to the motor according to a start of driving the motor, wherein a phase of the input signal of the specific pattern is determined on the basis of the stop position of the rotor. Other example embodiments may be provided.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.

Abstract: Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.

Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.

Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first and second nanowires disposed sequentially on the substrate in the first region, and extending respectively in a first direction, third and fourth nanowires disposed sequentially on the substrate in the second region, and extending respectively in the first direction, a first inner spacer between the first nanowire and the second nanowire, and including hydrogen of a first hydrogen mole fraction, and a second inner spacer between the third nanowire and the fourth nanowire, and including hydrogen of a second hydrogen mole fraction that is greater than the first hydrogen mole fraction.

Abstract: A semiconductor device and a method for forming a semiconductor are provided. The semiconductor device includes: a first substrate, a first conductive line disposed on the first substrate, a second substrate opposite to the first substrate, a second conductive line disposed on the second substrate and adjacent to the first conductive line, and a plurality of bonding structures between the first conductive line and the second conductive line. The first conductive line includes a plurality of first segments separated from one another. The second conductive line includes a plurality of second segments separated from one another. Each of the bonding structures is connected to a respective first segment of the plurality of first segments and a respective second segment of the plurality of second segments such that the plurality of first segments, the plurality of bonding structures and the plurality of second segments are connected in series.

Abstract: A water heating apparatus includes a sensor to detect an inflow water amount flowing into the water heating apparatus, and a controller to determine connection or disconnection between the water heating apparatus and a water storage tank, based on the inflow water amount flowing into the water heating apparatus for a preset time duration. Thus, the water heating apparatus determines whether or not the water storage tank is connected thereto based on the amount of inflow water introduced into the water heating apparatus. Then, the water heating apparatus determines the operation mode of the water heating apparatus based on the determination result. Thus, even when the user incorrectly sets the operation mode of the water heating apparatus, the water heating apparatus may actively and correctly operate.

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

Abstract: The present disclosure provides a sunroof system for a vehicle including glass slidably insertable into a vehicle body of the vehicle, and a passive radiant cooling layer disposed below the glass and slidably insertable into the vehicle body. The passive radiant cooling layer includes at least two layers among a first emission layer having a high emissivity in a first band relative to a band outside the first band, a second emission layer having a high emissivity in a second band, which is included in the first band and narrower than the first band, relative to a band outside the second band, and a reflection layer having a high reflectivity in a third band, which is a shorter wavelength than the first band, relative to a band outside the third band.

Abstract: The present disclosure relates to a method for manufacturing a positive electrode for a lithium-sulfur battery including: (1) mixing a sulfur-carbon composite and a binder to prepare a slurry for a positive electrode active material; (2) applying the slurry for the positive electrode active material to one surface of the current collector; (3) a first drying step of drying the current collector, to which the slurry is applied, using hot air and medium wave infrared radiation; and (4) a second drying step of drying the current collector, to which the slurry is applied, using a laser heat source after the first drying step (3).

Abstract: Provided are a printed circuit board and a method for manufacturing the same, the printed circuit board including: an insulating member; a first pad disposed in the insulating member; a plurality of first vias respectively disposed on a lower side of the first pad in the insulating member and connected to the first pad; and a second via disposed on an upper side of the first pad in the insulating member and connected to the first pad.

Abstract: The present invention relates to Myoviridae bacteriophage Vib-PAP-4(Accession No. KCTC 13168BP), isolated from nature, which possesses ability to specifically kill Vibrio parahaemolyticus bacteria and has the genome represented by SEQ ID No: 1, and a method for preventing infection of Vibrio parahaemolyticus bacteria and treating infection of Vibrio parahaemolyticus baceteria, using a composition containing the bacteriophage as an effective ingredient.