Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.

Abstract: An amplifier circuit for amplifying an input signal includes a transistor configured to receive the input voltage via an input port, and a second-harmonic trap connected between the transistor and ground, the second-harmonic trap having an impedance high enough to enable the second-harmonic trap to act as an open circuit at a second harmonic frequency of a voltage provided by the transistor. The second-harmonic trap includes a transformer including a primary winding connected to ground and a secondary winding, the primary winding receiving the voltage provided by the transistor. The second-harmonic trap further includes a variable capacitor connected in parallel with the secondary winding of the transformer, the variable capacitor having an adjustable capacitance that may be adjusted for the second-harmonic trap to act as the open circuit at the second harmonic frequency.

Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.

Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.

Abstract: An eye-examining apparatus in which a visible light optical system for observing a shape of an examinee's eye and an infrared optical system for detecting a shape of the cornea of the examinee's eye are integrated. The eye-examining apparatus having an integrated optical system comprises: an infrared light source for irradiating a cornea of the examinee's eye with infrared light; a visible light source for irradiating the eye with visible light; an image detector both for detecting an image of the infrared light which is irradiated from the infrared light source and reflected from the cornea of the eye and for detecting an image of the visible light which is irradiated from the visible light source to the eye; and a visible light blocking filter inserted in an optical path of the visible light and the infrared light traveling toward the image detector for blocking the visible light.

Abstract: A method of operating a memory device, a first setting signal is received by a first memory device among a plurality of memory devices. The first memory device has a first storage capacity, and the memory devices may be connected to one another by a single channel. A second setting signal is received by a second memory device among the plurality of memory devices. The second memory device has a second storage capacity different from the first storage capacity. N refresh operations are performed by the first memory device based on a first refresh command and the first setting signal during a first refresh period. M refresh operations are performed by the second memory device based on a second refresh command and the second setting signal during a second refresh period. A duration of the second refresh period is substantially the same as a duration of the first refresh period.

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

Abstract: A liquid crystal display includes: a first substrate on which a display area and a non-display area disposed on an outside of the display area are defined; a first insulating layer, which is disposed in the non-display area on the first substrate; a barrier pattern, which is disposed on the first insulating layer; a seal pattern, which is disposed on the barrier pattern to overlap the barrier pattern; and a second substrate, which is disposed to face the first substrate.

Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.

Abstract: A method for preparing acrylic acid, more specifically, to a method for preparing acrylic acid under a neutral condition at high yield in a short time without using a base, unlike the prior art in which a base is essentially used. The acrylic acid is produced using a supported catalyst having a specific composition when preparing acrylic acid by oxidation of allyl alcohol. Particularly, the preparation method can recover acrylic acid rather than acrylic acid salt as a final product, and thus has an advantage that the overall process cost can be reduced by eliminating essential processes in the prior art, such as ion exchange after the acidification process required for the conversion of acrylic acid salt to acrylic acid.

Abstract: Provided are a polarizer and a display device including a polarizer. The polarizer comprises: a base; a wire grid pattern layer disposed on the base and including wire patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; and a capping layer which is disposed on the wire grid pattern layer and comprises a first inorganic capping layer containing an inorganic material and an organic capping layer containing an organic material, wherein the first inorganic capping layer comprises inorganic capping patterns which are disposed on the wire grid pattern layer, extend in the first direction and are spaced apart from each other in the second direction and being disposed at positions corresponding to the wire patterns, and at least a portion of the organic capping layer is inserted into a space between adjacent inorganic capping patterns.

Abstract: Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

Abstract: Disclosed is an apparatus for decomposing low-concentration volatile organic compounds, which includes: an adsorption unit configured to adsorb a volatile organic compound; a heated air supply unit configured to supply a heated air to the adsorption unit; an oxidation decomposing catalyst unit configured to decompose a volatile organic compound detached from the adsorption unit; and an ozone supply unit configured to supply an ozone to the oxidation decomposing catalyst unit. The apparatus may maximize an exchange cycle semi-permanently by adsorbing low-concentration VOC under a high-flow condition and then detaching VOC within a short time and also by recycling an adsorption filter. In addition, the apparatus may effectively decompose VOC substances detached by a low flow into carbon dioxide and water under a condition with most excellent oxidation decomposition efficiency by using an oxidation decomposing catalyst filter.

Abstract: Disclosed herein are a secondary battery transfer apparatus for transferring a secondary battery in a secondary battery manufacturing process and a method for detecting a loading defect of a secondary battery in a carrier receiving the secondary battery. The secondary battery transfer apparatus includes a carrier having a receipt space to receive a secondary battery, a transfer unit transferring the carrier, a loading detection sensor sensing the secondary battery when the secondary battery inserted into the carrier reaches a designated height, and a controller receiving a result of sensing of the loading detection sensor and controlling operation of the transfer unit. The secondary battery transfer apparatus and the detection method detect whether or not a case of the secondary battery is damaged due to friction with the carrier and thus recognize a product defect in advance.

Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.

Abstract: A non-module type dual regulator assembly is provided. The assembly includes a pair of guide rails that are separated from each other and disposed in a door of a vehicle along a direction that a window glass is raised or lowered. A pair of glass holders are coupled to one side of the window glass and movably disposed on the respective guide rails. An upper connection member has a plurality of ends fastened to upper portions of the guide rails. A lower connection member has a plurality of ends fastened to lower portions of the guide rails. A cable is coupled to the glass holders and circulatably disposed on the guide rails to raise or lower the glass holders in the same direction at the same time. A driving motor is disposed in the lower connection member and circulates the cable.