Abstract: A memory apparatus may include an active control circuit and an internal voltage generation circuit. The active signal generation circuit may enable an internal active signal after a level of a second external power supply voltage is stabilized even when a normal active signal is enabled. The internal voltage generation circuit may generate an internal voltage from a first external power supply voltage based on the internal active signal.

Abstract: Provided is a method of manufacturing a secondary battery, in which scattering of an electrolyte is prevented while a degassing process is performed to prevent a product from being contaminated due to the scattering of the electrolyte. The method of manufacturing the secondary battery includes performing a formation process on a battery cell including a dead space to generate a gas within the battery cell, closing a piercing tool of a gas removing device to form a through hole in the dead space, thereby discharging the gas within the battery cell through the piercing tool, closing a sealing tool of the gas removing device after the gas is discharged to thermally bond an inner portion of the dead space that is adjacent to an electrode assembly within the battery cell, opening the piercing tool in the state where the sealing tool is closed, and opening the sealing tool after the piercing tool is opened.

Abstract: Disclosed is a catalyst filter, which includes a catalyst support and a nano metallic catalyst sprayed to a surface of the catalyst support. The catalyst filter uses catalyst slurry prepared by using a particulate catalyst, in which a small amount of nano metallic catalyst exhibiting a catalyst performance is sprayed to a surface of the catalyst support, different from an existing patent technique in which catalyst particles are formed and prepared as a support to consume a large amount of catalyst. Therefore, the specific surface area of the catalyst filter is not smaller than the specific surface area of the nano catalyst particles, and thus the catalyst filter may effectively remove and decompose ultra-low concentration gas-state contaminants in an indoor air.

Abstract: A semiconductor circuit includes a first circuit determining a voltage of a first node in response to the clock signal and the input data signal, a first latch determining a voltage of a second node in response to the clock signal and the voltage of the first node, and a second circuit determining a voltage of a third node in response to the clock signal and the voltage of the second node. The output data signal is provided in response to the voltage of the third node, the clock signal controls a flip-flop operation with respect to the input data signal and the output data signal, and respective voltages are maintained constant at the first node, second node and third node regardless of level transitions in the clock signal so long as a level of the input data signal is maintained constant.

Abstract: An organic light-emitting display device according to an embodiment includes a light-emitting structure. The light-emitting structure includes a lower electrode, an organic light-emitting layer, and an upper electrode, which are stacked one above another in sequence. The organic light-emitting display device further includes a bank insulating layer covering the edge of the lower electrode. The organic light-emitting layer extends onto the bank insulating layer. The organic light-emitting layer includes a side surface being vertically aligned with a side surface of the bank insulating layer.

Abstract: An organic light-emitting display device includes an organic insulating layer such as an over-coat layer, a bank insulating layer and a capping layer. The organic insulating layer extends onto a non-display area of a lower substrate. The organic insulating layer is in contact with an encapsulating layer having a moisture-absorbing material on the non-display area of the lower substrate. Thus, the organic light-emitting display may block a path of permeating the moisture by the organic insulating layer.

Abstract: Disclosed is a melt-blown fiber web with improved concentration force and elasticity, whereby a melt-blown fabric is cut and sealed at predetermined intervals using knives having arbitrary patterns so that concentration force and elasticity of the melt-blown fiber web can be improved without degrading the inherent function of the fiber web. Further disclosed are a method and apparatus for manufacturing the melt-blown fiber web. The melt-blown fiber web includes thermoplastic filaments, wherein cutting portions and sealing portions are arranged on top and bottom surfaces of the fiber web at predetermined intervals along a thickness of the fiber web so that a concentration force and elasticity of the fiber web are improved.

Abstract: Provided are a bi-cell for a secondary battery having improved stability which may reduce shrinkage of a separator, and a method of preparing the bi-cell. The bi-cell for a secondary battery having improved stability according to an exemplary embodiment of the present invention is characterized in that a cathode and an anode are alternatingly disposed in a state in which the cathode has one more layer than the anode or the anode has one more layer than the cathode, separators having a bigger size than the cathode and the anode and insulating the cathode and the anode are disposed between the cathode and the anode, and edges of an upper separator and edges of a lower separator, which face to each other having the cathode and the anode disposed therebetween, are attached to each other to form fused portions.

Abstract: The present invention relates to an electric anticorrosive potential measurement electrode unit for measuring an anticorrosive potential of an anticorrosive object (30) buried underground, and comprises: a first electrode unit (10) buried underground near the anticorrosive object (30); and a second electrode unit (20) buried so as to be separated by a distance (D) from the first electrode unit (10) and measuring a comparative potential relative to the first electrode unit (10).

Abstract: The present invention relates to a display device having an integral self-capacitance touch sensor, which can enhance a display property and touch performance by reducing parasitic capacitance and resistance, comprising: a plurality of gate lines and a plurality of data lines that are arranged on a first substrate to cross each other; a plurality of pixel electrodes that are connected to the plurality of gate lines and data lines; a plurality of common and touch electrodes, each of which is formed to overlap some of the plurality of pixel electrodes; and a plurality of routing wires connected to the plurality of common and touch electrodes, respectively, to extend parallel to each other, wherein the plurality of routing wires overlap the data lines with a first insulation film therebetween for covering the data lines, or overlap the gate lines that cross the data lines, and the common and touch electrodes are connected to the routing wires, respectively, through contact holes formed through a second insulatio

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

Abstract: A display device includes a display panel, an optical film arranged on an upper portion of the display panel and including first and second intaglio pattern portions having different depths from each other, a bonding member configured to contact at least a part of the display panel and a surface of the first intaglio pattern portion and an air layer configured to fill between a surface of the second intaglio pattern portion and the display panel.

Abstract: A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

Abstract: A method for manufacturing a display panel includes providing a mother substrate that includes a display area and a non-display area, and includes a first substrate, a second substrate facing the first substrate, and a sealant provided between the first substrate and the second substrate, generating a crack on the sealant through irradiation of laser onto the sealant between the first substrate and the second substrate, and cutting a part of the second substrate and a part of the sealant at a position corresponding to the crack.

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

Abstract: Exemplary embodiments may disclose a flip-flop circuit for inserting a zero-delay bypass mux including a master circuit which is configured to receive a data input, an input clock signal, and a bypass signal, and output an intermediate signal to a first node; and a slave circuit which is configured to receive the intermediate signal at the first node, the input clock signal, and the bypass signal, and output an output clock signal. The bypass signal controls the slave circuit to output one of a buffered input clock signal and a stretched clock signal as the output clock signal based on a logic level of the bypass signal.

Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

Abstract: A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.

Abstract: An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.