Abstract: Herein is provided a protective layer for a plasma display panel and a method of forming the protective layer. The protective layer is formed on a substrate of the plasma display panel which includes sustain electrodes. Grain columns having directionality are formed in the texture of the protective layer. Because the direction of the grain columns can be controlled, the general orientation of the voids is known, and an electric field can be applied for discharge in a direction where the number of voids is smallest. As a result, the etching rate of the protective layer can be reduced, thereby increasing the lifetime of the protective layer. In addition, since discharge ions are less likely to impact the protective layer rapid emission of secondary electrons and reduced discharge delay time is realized. It is therefore possible to shorten the discharge delay time and to improve the breakdown voltage of discharge.

Abstract: A method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process. The method includes the steps of: forming a plurality of conductive structures on a substrate; forming an etch stop layer and a flowable insulation layer on the plurality of conductive structures subsequently; forming a photoresist pattern on the flowable insulation layer; forming a plurality of contact holes by etching the flowable insulation layer with use of the photoresist pattern as an etch mask, thereby exposing portions of the etch stop layer; forming at least one barrier layer on the contact holes; removing said at least one barrier layer and the etch stop layer disposed at each bottom portion of the contact holes to thereby expose the substrate; and cleaning the contact holes.

Abstract: Disclosed is a method for forming a plurality of contact holes in a semiconductor device. The method includes the steps of: forming an oxide-based layer on a substrate; forming an organic polymer layer on the oxide-based layer; forming a photoresist pattern on the organic polymer layer to form the plurality of contact holes; etching the organic polymer layer by using the photoresist pattern as an etch mask, thereby forming a hard mask; etching the oxide-based layer by using the photoresist pattern and the hard mask as an etch mask; and removing the photoresist pattern and the hard mask by performing a photoresist strip process, thereby obtaining the plurality of contact holes.

Abstract: Provided is a protective layer formed using at least one selected from the group consisting of a magnesium oxide and a magnesium salt and at least one selected from the group consisting of a lithium salt, a lithium oxide, a germanium oxide, and a germanium element. Provided is also a composition for forming a protective layer. When the composition is used for a protective layer of a gas discharge display device, an electrode or a dielectric can be protected from plasma ions generated by discharge of a mixed gas of Ne+Xe or He+Ne+Xe, a lower discharge voltage and a shorter discharge lag time can be obtained.

Abstract: The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved tolerance to a wet cleaning process. For a contact formation such as a gate structure, a bit line or a metal wire, a spin on glass (SOG) layer employed as an inter-layer insulation layer becomes tolerant to the wet cleaning process by allowing even a bottom part of the SOG layer to be densified during a curing process. The SOG layer is subjected to the curing process after a maximum densification thickness of the SOG layer is obtained through a partial removal of the initially formed SOG layer or through a multiple SOG layer each with the maximum densification thickness. After the SOG layer is cured, a self-aligned contact etching process is performed by using a photoresist pattern singly or together with a hard mask.

Abstract: A method for fabricating a semiconductor device is capable of preventing a hard mask layer of a conductive structure from being damaged during a self-aligned contact etching process. The method includes the steps of: forming a plurality of conductive structures including a conductive layer and a hard mask layer on a substrate; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; and performing a self-aligned contact (SAC) etching process selectively etching the inter-layer insulation layer, the etch stop layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer.

Abstract: Disclosed is a method for fabricating a semiconductor device having at least one contact holes formed by employing a self-aligned contact (SAC) etching process. The contact holes are formed through the shortened number of sequential steps by using different process recipes. First, an anti-reflective coating (ARC) layer formed on a substrate structure prepared sequentially with a substrate, conductive structures, an etch stop layer and an inter-layer insulation layer is etched by employing an etch gas of CF4, O2, CO and Ar. Then, a portion of an inter-layer insulation layer is etched with use of an etch gas of CF4 and O2. The rest portion of the inter-layer insulation layer is subsequently etched by using a different etch gas of C4F6, CH2F2, O2 and Ar to thereby form at least one contact hole exposing the etch stop layer.

Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.

Abstract: Disclosed is a method for fabricating a semiconductor device with protected conductive structures. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask insulation layer formed on the conductive layer; forming a first insulation layer on the conductive structures; forming a plurality of plugs contacted to the substrate disposed between the conductive structures by passing through the first insulation layer and having a predetermined height corresponding to a height between the conductive layer and a top of the hard mask insulation layer; forming an attack barrier layer covering top and sidewalls of the hard mask insulation layer; forming a second insulation layer on the attack barrier layer; and selectively etching the second insulation layer to form a contact hole exposing at least one of the plugs.

Abstract: Disclosed is a method for fabricating a semiconductor device having at least one contact holes formed by employing a self-aligned contact (SAC) etching process. The contact holes are formed through the shortened number of sequential steps by using different process recipes. First, an anti-reflective coating (ARC) layer formed on a substrate structure prepared sequentially with a substrate, conductive structures, an etch stop layer and an inter-layer insulation layer is etched by employing an etch gas of CF4, O2, CO and Ar. Then, a portion of an inter-layer insulation layer is etched with use of an etch gas of CF4 and O2. The rest portion of the inter-layer insulation layer is subsequently etched by using a different etch gas of C4F6, CH2F2, O2 and Ar to thereby form at least one contact hole exposing the etch stop layer.

Abstract: A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive structures are first planarized. Then, a hard mask made of a nitride-based material is formed by using a photoresist pattern and an anti-reflective coating layer as an etch mask. After the hard mask formation, the photoresist pattern and the anti-reflective coating layer are removed. Subsequently, a SAC etching process is performed to etch the inter-layer insulation layer with use of the hard mask as an etch mask, thereby obtaining a contact hole exposing the etch stop layer disposed between the conductive structures. The exposed etch stop layer is removed through the use of a blanket etch-back process, and a cleaning process is applied thereafter.

Abstract: The present invention relates to a method for fabricating a semiconductor device with a fine pattern. The method includes the steps of: (a) forming a semiconductor substrate structure including a substrate, a nitride layer for forming a hard mask, a plurality of conductive patterns, an etch stop layer, an inter-layer insulation layer, an anti-reflective coating (ARC) layer and a photoresist pattern; (b) selectively etching the ARC layer and the nitride layer with use of the photoresist pattern as an etch mask to form a hard mask; (c) removing the photoresist pattern and the ARC layer; (d) etching the inter-layer insulation layer disposed between the conductive patterns by using the hard mask as an etch mask to form a contact hole exposing the etch stop layer; (e) removing the etch stop layer formed at a bottom area of the contact hole to expose the substrate; and (f) forming a plug electrically contacted to the exposed substrate, wherein the steps (b) and (d) to (e) proceeds in an in situ condition.

Abstract: A method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process. The method includes the steps of: forming a plurality of conductive structures on a substrate; forming an etch stop layer and a flowable insulation layer on the plurality of conductive structures subsequently; forming a photoresist pattern on the flowable insulation layer; forming a plurality of contact holes by etching the flowable insulation layer with use of the photoresist pattern as an etch mask, thereby exposing portions of the etch stop layer; forming at least one barrier layer on the contact holes; removing said at least one barrier layer and the etch stop layer disposed at each bottom portion of the contact holes to thereby expose the substrate; and cleaning the contact holes.

Abstract: Disclosed is a method for fabricating a semiconductor device with an improved tolerance to a wet cleaning process. For a contact formation such as a gate structure, a bit line or a metal wire, a spin on glass (SOG) layer employed as an inter-layer insulation layer becomes tolerant to the wet cleaning process by allowing even a bottom part of the SOG layer to be densified during a curing process. The SOG layer is subjected to the curing process after a maximum densification thickness of the SOG layer is obtained through a partial removal of the initially formed SOG layer or through a multiple SOG layer each with the maximum densification thickness. After the SOG layer is cured, a self-aligned contact etching process is performed by using a photoresist pattern singly or together with a hard mask.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of first plugs contacted to a substrate by passing through a first inter-layer insulation layer; forming a second inter-layer insulation layer on the first plugs; forming a conductive pattern contacted to a group of the first plugs by etching selectively the second inter-layer insulation layer; and forming a contact hole exposing a surface of the first plug that is not contacted to the conductive pattern by etching selectively the second insulation layer with use of a dry-type and wet-type etch process, wherein an attack barrier layer is formed on between the first inter-layer insulation layer and the second inter-layer insulation layer to thereby prevent an incidence of attack to the first interlayer insulation layer contacted to the first plug during the wet-type etch process for forming the contact hole.

Abstract: A method for fabricating a semiconductor device capable of preventing an electric short circuit between a storage node contact plug and a conductive pattern by forming an attack barrier layer or use of an insulation layer having a flow-fill property. The attack barrier layer for preventing the electric short circuit is formed by employing two methods. First, the attack barrier layer is formed on an entire surface of a structure containing the plugs after the CMP process and the cleaning process. Second, the attack barrier layer is formed on a structure including a storage node contact hole such that the attack barrier layer fills the lost portion of the insulating material-based layer. Also, instead of using the attack barrier layer, the insulation layer having a flow-fill property is deposited after the cleaning process.

Abstract: The present invention relates to a method for fabricating a semiconductor device with realizable advanced fine patterns.

Abstract: The present invention is related to a method for fabricating a semiconductor device capable of preventing occurrences of void and seam phenomena caused by a negative slope of an insulation layer or a bowing profile phenomenon in a cross-sectioned etch profile of a contact hole. To achieve this effect, the attack barrier layer or the capping layer is additionally deposited on the profile containing self-aligned contact holes in order to prevent an undercut of the inter-layer insulation layer, which is a main cause of the seam generations. Also, the attack barrier layer has a function of preventing the inter-layer insulation layer from being attacked during the wet cleaning/etching process. Ultimately, it is possible to improve device characteristics with the prevention of the seam generations.

Abstract: A method for fabricating a semiconductor device includes the steps of: (a) forming a plurality of conductive patterns on a substrate in a cell region and a peripheral circuit region; (b) forming an insulation layer on an entire surface of the resulting structure from the step. (a); (c) forming a plurality of plugs in the cell region and simultaneously forming a dummy pattern in a region between the cell region and the peripheral circuit region, each plug and the dummy pattern being contacted to the substrate allocated between the conductive patterns by passing through the insulation layer; (d) forming a photoresist pattern masking the resulting structure in the cell region; and (e) removing the insulation layer in the peripheral circuit region by performing a wet etching process with use of the photoresist pattern as an etch mask to thereby expose a surface of the substrate in the peripheral circuit region.