Abstract: A method for fabricating a semiconductor device includes forming an etch barrier layer over a semi-finished substrate that includes a plurality of patterns, forming an insulation layer over the etch barrier layer, planarizing the insulation layer, recessing a portion of the planarized insulation layer, forming a hard mask pattern over the recessed and planarized insulation layer, etching the recessed insulation layer to form a contact hole, etching the etch barrier layer formed over a bottom portion of the contact hole, and forming a plug contact in the contact hole.

Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.

Abstract: A device is proposed for producing high-frequency microwaves, having a cathode arrangement with heatable cathodes for emitting electrons, two grating arrangements for controlling and focusing the electrons flow and an anode for recaiving the electrons passing through the grating arrangements. The cathode arrangement and the first grating arrangement and also a blocking or choke element define an output cavity forming a resonance cavity and the anode and the second grating arrangement define an output cavity likeeise forming a resonance cavity. The cathode arrangement has a monuting for the cathode such that deformation of the cathode with reduction of the spacing between the heatable cathode and grating is avoided.

Abstract: A method for fabricating a semiconductor device includes forming a first pattern over a substrate, forming an oxide-based layer over the first pattern, forming a hard mask layer over the oxide-based layer, etching the hard mask layer at a first substrate temperature, and etching the oxide-based layer to form a second pattern, wherein the oxide-based layer is etched at a second substrate temperature which is greater than the first substrate temperature using a gas including fluorine (F) and carbon (C) as a main etch gas.

Abstract: A method for fabricating a semiconductor device includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, filling a space between the electrode patterns, planarizing the insulation layer until shoulder portions of the hard mask are planarized, forming a mask pattern on a resultant structure, and etching a portion of the insulation layer to form a contact hole.

Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a plurality of bit line patterns, each bit line pattern including a bit line hard mask formed over a bit line conductive layer, forming an inter-layer insulation layer filled between the bit line patterns, planarizing the inter-layer insulation layer until top portions of the bit line hard masks are exposed, partially etching the inter-layer insulation layer to form first open regions, enlarging a width of the first open regions, forming a capping layer to cover the top portions of the bit line hard masks and to cover a surface of the first open regions, etching the capping layer and remaining portions of the inter-layer insulation layer between the bit line patterns to form second open regions below the first open regions, and forming storage node contacts filling in the first and second open regions.

Abstract: Disclosed is a method for fabricating a semiconductor device with protected conductive structures. The method includes the steps of: forming a plurality of conductive structures on a substrate, each conductive structure including a conductive layer and a hard mask insulation layer formed on the conductive layer; forming a first insulation layer on the conductive structures; forming a plurality of plugs contacted to the substrate disposed between the conductive structures by passing through the first insulation layer and having a predetermined height corresponding to a height between the conductive layer and a top of the hard mask insulation layer; forming an attack barrier layer covering top and sidewalls of the hard mask insulation layer; forming a second insulation layer on the attack barrier layer; and selectively etching the second insulation layer to form a contact hole exposing at least one of the plugs.

Abstract: A method for fabricating a semiconductor device is capable of preventing a hard mask layer of a conductive structure from being damaged during a self-aligned contact etching process. The method includes the steps of: forming a plurality of conductive structures including a conductive layer and a hard mask layer on a substrate; sequentially forming a first nitride layer, an oxide layer, a second nitride layer, and an etch stop layer on the plurality of conductive structures; forming an inter-layer insulation layer on the etch stop layer; and performing a self-aligned contact (SAC) etching process selectively etching the inter-layer insulation layer, the etch stop layer, the second nitride layer and the oxide layer until the SAC etching process is stopped at the first nitride layer to thereby form a contact hole exposing the first nitride layer.

Abstract: A Plasma Display Panel (PDP) includes a dielectric layer having a plurality of dielectric-layer perforated holes arranged in a matrix; and upper and lower electrode layers having electrode-layer perforated holes connected to the dielectric-layer perforated holes and arranged on both surfaces of the dielectric layer; the upper electrode layer includes a plurality of first electrodes extending in a first direction, the plurality of first electrodes surrounding a group of electrode-layer perforated holes arranged in the first direction; and the lower electrode layer includes a plurality of second electrodes extending in a second direction different from the first direction, the plurality of second electrodes surrounding a group of electrode-layer perforated holes arranged in the second direction.

Abstract: A method for fabricating a semiconductor device includes the steps of: (a) forming a plurality of conductive patterns on a substrate in a cell region and a peripheral circuit region; (b) forming an insulation layer on an entire surface of the resulting structure from the step. (a); (c) forming a plurality of plugs in the cell region and simultaneously forming a dummy pattern in a region between the cell region and the peripheral circuit region, each plug and the dummy pattern being contacted to the substrate allocated between the conductive patterns by passing through the insulation layer; (d) forming a photoresist pattern masking the resulting structure in the cell region; and (e) removing the insulation layer in the peripheral circuit region by performing a wet etching process with use of the photoresist pattern as an etch mask to thereby expose a surface of the substrate in the peripheral circuit region.

Abstract: A method for forming a contact hole in a semiconductor device is provided. A method for forming a contact hole in a semiconductor device includes: forming an insulation layer over a bottom structure; forming a hard mask pattern over the insulation layer; etching a portion of the insulation layer using the hard mask pattern as an etch mask to form an opening; forming spacers over sidewalls of the hard mask pattern and the insulation layer patterned by the etching; etching a remaining portion of the insulation layer to form a contact hole exposing a portion of the bottom structure; and removing the spacers and the hard mask pattern.

Abstract: A method for fabricating a semiconductor device capable of preventing a hard mask from being lifted and patterns from being defective. Particularly, an inter-layer insulation layer and an etch stop layer formed on a substrate structure provided with conductive structures are first planarized. Then, a hard mask made of a nitride-based material is formed by using a photoresist pattern and an anti-reflective coating layer as an etch mask. After the hard mask formation, the photoresist pattern and the anti-reflective coating layer are removed. Subsequently, a SAC etching process is performed to etch the inter-layer insulation layer with use of the hard mask as an etch mask, thereby obtaining a contact hole exposing the etch stop layer disposed between the conductive structures. The exposed etch stop layer is removed through the use of a blanket etch-back process, and a cleaning process is applied thereafter.

Abstract: Disclosed is a method for forming a polysilicon plug of a semiconductor device.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming at least two gate patterns over a substrate; forming a first sidewall layer over on entire of the substrate structure including gat patterns; forming an insulation layer over the first sidewall layer; selectively removing the insulation layer between the gate patterns to form a contact hole partially exposing the first sidewall layer; forming a second sidewall layer over the first sidewall layer exposed by the contact hole; and removing the first and the second sidewall layers disposed at a bottom portion of the contact hole to expose a selected portion of the substrate between the gate patterns.

Abstract: A protecting layer of a Plasma Display Panel (PDP) is composed of metal and metal oxide. The metal is disposed away from the surface of the protecting layer by 10% or less than the thickness of the protecting layer. Furthermore, in a method of forming the protecting layer for a PDP and in a PDP employing the protecting layer, the metal is disposed away from the surface of the protecting layer by 10% or less than the thickness of the protecting layer.

Abstract: A protecting layer is formed of a magnesium oxide and at least one additional component selected from the group consisting of a copper component selected from copper and a copper oxide, a nickel component selected from nickel and a nickel oxide, a cobalt component selected from cobalt and a cobalt oxide, and an iron component selected from iron and an iron oxide; a composite for forming the protecting layer; a method of forming the protecting layer; and a plasma display panel including the protecting layer. The protecting layer, which is used in a PDP, protects an electrode and a dielectric layer from a plasma ion generated by a gaseous mixture of Ne and Xe, or He, Ne, and Xe, and discharge delay time and dependency of the discharge delay time on temperature can be decreased and sputtering resistance can be increased.

Abstract: The present invention relates to a method for fabricating a semiconductor device with a fine pattern. The method includes the steps of: (a) forming a semiconductor substrate structure including a substrate, a nitride layer for forming a hard mask, a plurality of conductive patterns, an etch stop layer, an inter-layer insulation layer, an anti-reflective coating (ARC) layer and a photoresist pattern; (b) selectively etching the ARC layer and the nitride layer with use of the photoresist pattern as an etch mask to form a hard mask; (c) removing the photoresist pattern and the ARC layer; (d) etching the inter-layer insulation layer disposed between the conductive patterns by using the hard mask as an etch mask to form a contact hole exposing the etch stop layer; (e) removing the etch stop layer formed at a bottom area of the contact hole to expose the substrate; and (f) forming a plug electrically contacted to the exposed substrate, wherein the steps (b) and (d) to (e) proceeds in an in situ condition.

Abstract: Provided are a protective layer made of magnesium oxide containing at least one rare earth element selected from the group consisting of the rare earth elements, in which the content of the at least one rare earth element is from about 5.0×10?5 to about 6.0×10?4 per 1 part by weight of the magnesium oxide, a composite for forming the protective layer, a method of forming the protective layer, and a plasma display panel including the protective layer. The protective layer can reduce a discharge delay time and the temperature dependency of the discharge delay time, and thus, is suitable for single scan and an increase in Xe content.

Abstract: The present invention relates to a method for fabricating a semiconductor device with realizable advanced fine patterns.

Abstract: Disclosed is a method for fabricating a semiconductor device. The method includes the steps of: forming a plurality of conductive patterns on a substrate; depositing an insulation layer on the substrate; recessing the insulation layer until a vertical height of the insulation layer becomes lower than that of the plurality of conductive patterns; forming an etch stop layer in the form of sidewalls of the conductive patterns; forming a mask pattern over the etch stop layer; and forming a plurality of contact holes such that etch profiles of the plurality of contact holes are aligned with the plurality of conductive patterns and the substrate is exposed by etching the insulation layer by using the mask pattern as an etch mask.