Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.

Abstract: A method for manufacturing a semiconductor memory device includes sequentially depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer, etching the mask layer and forming a mask pattern, etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier, etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier, and etching the bottom electrode layer by using the first top electrode layer as an etch barrier.

Abstract: An apparatus for managing a delay in receiving a three-dimensional (3D) image may include an image receiver to receive a left image and a right image for 3D image synthesis, and a substitution content output unit to output substitution content during a waiting time caused by a difference between points in time at which the left image and the right image are received.

Abstract: An apparatus and a method for synchronizing left and right streams in a stationary/mobile hybrid 3DTV are disclosed. The apparatus according to an exemplary embodiment may synchronize content streams corresponding to left and right images using a timestamp pairing mode, a timestamp offset mode, and a network time protocol (NTP) synchronization mode.

Abstract: Provided is a video providing method and a video playing method for a three-dimensional (3D) video, and an apparatus for performing the methods. The video providing method may transmit a reconstruction mode for reconstructing a low-resolution additional video having lower resolution than a high-resolution reference video.

Abstract: A content providing apparatus and method, and a content reproduction apparatus and method for accessing a content stream in a hybrid three-dimensional television (3DTV) are disclosed. The content providing apparatus may include a content stream generation unit to generate a first content stream corresponding to a reference image and a second content stream corresponding to a supplementary image, a descriptor generation unit to generate a descriptor associated with the first content stream and the second content stream, and a data transmission unit to transmit the first content stream, the second content stream, and the descriptor to a content reproduction apparatus.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.

Abstract: A method for fabricating a semiconductor device includes forming a bottom-electrode metal layer over a substrate, planarizing the bottom-electrode metal layer by a first thickness through a chemical mechanical polishing (CMP) process, etching the bottom-electrode metal layer by a second thickness through a wet etching process, forming a plurality of layers of a magnetic tunneling junction (MTJ) element over the bottom-electrode metal layer, forming a top electrode over the plurality of layers, and forming the MTJ element and a bottom electrode by etching the plurality of layers and the bottom-electrode metal layer using the top electrode as an etch mask.

Abstract: A method for manufacturing a semiconductor memory device includes sequentially depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer, etching the mask layer and forming a mask pattern, etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier, etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier, and etching the bottom electrode layer by using the first top electrode layer as an etch barrier.

Abstract: Disclosed herein is a stable liquid formulation comprising human growth hormone; L-lysine, L-arginine or polyethylene glycol 300; and poly(oxyethylene) poly(oxypropylene) copolymer, polyethylene glycol-15 polyoxystearate or polyethylene glycol-35 castor oil.

Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern.

Abstract: Provided are a protecting layer for a plasma display panel (PDP), a method of forming the same, and a PDP including the protecting layer. The protecting layer includes a magnesium oxide-containing layer having a surface to which magnesium oxide-containing particles having a magnesium vacancy-impurity center (VIC) are attached. The protecting layer is resistant to plasma ions and has excellent electron emission effects, and thus, a PDP including the protecting layer can be operated at low voltage with high discharge efficiency.

Abstract: A method of fabricating a semiconductor device, the method includes forming gate patterns on a substrate, recessing the substrate between the gate patterns, thereby forming a first resulting structure including recesses, forming a gate spacer layer on an entire surface of the first resulting structure including the gate patterns, etching the gate spacer layer at a bottom of the recess, and forming a plug on the recess, thereby forming a second resulting structure including the plug.

Abstract: A method for fabricating a semiconductor device with a vertical channel includes providing a substrate over which a hard mask pattern is formed, forming pillars over the substrate using the hard mask pattern thereby forming a resultant structure, forming an insulation layer over the resultant structure, planarizing the hard mask pattern and the insulation layer until the pillars are exposed, and forming a storage electrode over the exposed pillars.

Abstract: A method for manufacturing a semiconductor memory device includes sequentially depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer, etching the mask layer and forming a mask pattern, etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier, etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier, and etching the bottom electrode layer by using the first top electrode layer as an etch barrier.

Abstract: A protective layer of a plasma display panel includes smoky magnesium oxide, the smoky magnesium oxide having single crystal magnesium oxide with a plurality of cavities therein.

Abstract: A method for fabricating a semiconductor device includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, filling a space between the electrode patterns, planarizing the insulation layer until shoulder portions of the hard mask are planarized, forming a mask pattern on a resultant structure, and etching a portion of the insulation layer to form a contact hole.

Abstract: A Plasma Display Panel (PDP) includes a dielectric layer having a plurality of dielectric-layer perforated holes arranged in a matrix; and upper and lower electrode layers having electrode-layer perforated holes connected to the dielectric-layer perforated holes and arranged on both surfaces of the dielectric layer; the upper electrode layer includes a plurality of first electrodes extending in a first direction, the plurality of first electrodes surrounding a group of electrode-layer perforated holes arranged in the first direction; and the lower electrode layer includes a plurality of second electrodes extending in a second direction different from the first direction, the plurality of second electrodes surrounding a group of electrode-layer perforated holes arranged in the second direction.