Abstract: A touch panel including a substrate and a touch element is provided. The substrate has a predetermined number of touch areas. The touch element is disposed in the predetermined number of touch areas and includes a plurality of first electrodes, a plurality of second electrodes, and the predetermined number of third electrodes. Each third electrode includes a plurality of third electrode patterns and a plurality of third connection portions. Each third connection portion electrically insulatingly intersects at least one of the first electrodes or at least one of the second electrodes and electrically connects two adjacent third electrode patterns. Several of the first electrodes arranged in a first direction and corresponding to different touch areas are electrically connected, and several of the second electrodes arranged in a second direction and corresponding to different touch areas are electrically connected.

Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.

Abstract: This invention discloses an LED lamp with an external light source, including a tube, an LED light source plate. The LED light source plate includes a strip base and a plurality of LED illuminants. The lamp has a strip through hole along the length direction of the lamp. The strip base is fixed to the external circumference surface of the lamp, the plurality of LED illuminants are placed between the two side surfaces of the strip through hole. Preferably, the lamp is a circular glass lamp, the strip through hole is on the top of the lamp. Furthermore, the inner surface of the lamp is covered with a diffusion layer. The present invention is beneficial for automatic production and reducing the cost. At the same time, the LED light has a good diffusion and the waste heat is easy to dissipate.

Abstract: A vertical furnace includes a heat treatment tube, at least one reactive gas inlet, first adiabatic plates and second adiabatic plates. The at least one reactive gas inlet is disposed at or near a bottom end of the heat treatment tube. The first adiabatic plates are stacked in the heat treatment tube, each of the first adiabatic plates having a flow channel structure for allowing a gas to pass through, in which all the corners in the flow channel structure are rounded. The second adiabatic plates are stacked below the first adiabatic plates in the heat treatment tube.

Abstract: This invention discloses an LED lamp with an external light source, including a tube, an LED light source plate. The LED light source plate includes a strip base and a plurality of LED illuminants. The lamp has a strip through hole along the length. direction of the lamp. The strip base is fixed to the external circumference surface of the lamp, the plurality of LED illuminants are placed between the two side surfaces of the strip through hole. Preferably, the lamp is a circular glass lamp, the strip through hole is on the top of the lamp. Furthermore, the inner surface of the lamp is covered with a diffusion layer. The present invention is beneficial for automatic production and reducing the cost. At the same time, the LED light has a good diffusion and the waste heat is easy to dissipate.

Abstract: The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.

Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a bottom electrode layer over a substrate and forming a first passivation layer over the bottom electrode layer by a first atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a dielectric layer over the first passivation layer by a second atomic layer deposition process and forming a second passivation layer over the dielectric layer by a third atomic layer deposition process. The method for manufacturing a semiconductor structure further includes forming a top electrode layer over the second passivation layer.

Abstract: A method for preparing a phenol-formaldehyde resin is provided. The method includes extracting a biomass pyrolysis oil to obtain a first phenolic mixture, mixing the first phenolic mixture, furfural and an alkaline catalyst to proceed to a first polymerization reaction to form a phenol-formaldehyde resin precursor solution, and adding the alkaline catalyst to the phenol-formaldehyde resin precursor solution to proceed to a second polymerization reaction to form a phenol-formaldehyde resin solution. The disclosure also provides a resin material prepared from the phenol-formaldehyde resin. The disclosure further provides a method for preparing a resin molding material.

Abstract: A color changeable textile is formed by weaving a front yarn and a rear yarn. The front yarn forms plural front loops connected to each other. The rear yarn forms plural rear loops connected to each other. The rear yarn further coupled to a portion of the front loops to link the rear loops to the front loops. The color changeable textile shows the color of the front yarn at the front surface when there is no extra force applied to the color changeable textile. A part of the color changeable textile reveals the color of the rear yarn when the color changeable textile is stretched.

Abstract: A method of handling a short message re-delivery for a network entity of a wireless communication system includes receiving a request corresponding to a transmission failure of a short message transmitted to a communication device without a Mobile Subscriber Integrated Services Digital Network Number (MSISDN); generating a first correlation identification (ID) according to the request; and storing the first correlation ID with a short message service center (SMSC) address corresponding to the short message.

Abstract: The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.

Abstract: The present disclosure relates to a MIM capacitor, and an associated method of formation. In some embodiments, the MIM capacitor has a first electrode having a bottom capacitor metal layer disposed over a semiconductor substrate. A second electrode having a middle capacitor metal layer overlies the bottom capacitor metal layer. A third electrode having a top capacitor metal layer has a stepped structure is laterally and vertically separated from the middle capacitor metal layer by a capacitor dielectric layer continuously extends from a first position between the bottom capacitor metal layer and the middle capacitor metal layer, to a second position between the middle capacitor metal layer and the top capacitor metal layer. The capacitor dielectric layer allows for the MIM capacitor to have a structure that improves fabrication of the capacitor.

Abstract: The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor, and an associated method of formation. In some embodiments, the MIM capacitor includes a first electrode having a capacitor bottom metal layer disposed over a dielectric buffer layer located over an under-metal layer. A capacitor dielectric layer is disposed onto and in direct contact with the capacitor bottom metal layer. A second electrode having a top capacitor metal layer is disposed onto and in direct contact with the capacitor dielectric layer. A capacitor inter-level dielectric (ILD) layer is disposed over the top capacitor metal layer, and a substantially planar etch stop layer disposed over the capacitor ILD layer. The capacitor's simple stack provides for a small step size that prevents topography related issues, while the dielectric buffer layer removes design restrictions on the lower metal layer.

Abstract: A vertical furnace includes a heat treatment tube, at least one reactive gas inlet, first adiabatic plates and second adiabatic plates. The at least one reactive gas inlet is disposed at or near a bottom end of the heat treatment tube. The first adiabatic plates are stacked in the heat treatment tube, each of the first adiabatic plates having a flow channel structure for allowing a gas to pass through, in which all the corners in the flow channel structure are rounded. The second adiabatic plates are stacked below the first adiabatic plates in the heat treatment tube.

Abstract: A method of handling a short message re-delivery for a network entity of a wireless communication system includes receiving a request corresponding to a transmission failure of a short message transmitted to a communication device without a Mobile Subscriber Integrated Services Digital Network Number (MSISDN) ; generating a first correlation identification (ID) according to the request; and storing the first correlation ID with a short message service center (SMSC) address corresponding to the short message.

Abstract: A method for preparing a phenol-formaldehyde resin is provided. The method includes extracting a biomass pyrolysis oil to obtain a first phenolic mixture, mixing the first phenolic mixture, furfural and an alkaline catalyst to proceed to a first polymerization reaction to form a phenol-formaldehyde resin precursor solution, and adding the alkaline catalyst to the phenol-formaldehyde resin precursor solution to proceed to a second polymerization reaction to form a phenol-formaldehyde resin solution. The disclosure also provides a resin material prepared from the phenol-formaldehyde resin. The disclosure further provides a method for preparing a resin molding material.

Abstract: A method of handling a message service for an Internet Protocol-Short-Message-Gateway (IP-SM-GW) of a wireless communication system comprises requesting routing information of a terminating device in the wireless communication system from a home subscriber server (HSS)/home location register (HLR) of the wireless communication system for a message, wherein the terminating device is attached to a mobility management entity (MME) of the wireless communication system and is registered with short message service (SMS) in MME; and transmitting the short message to the MME via an interface according to the routing information.

Abstract: A method for preparing a phenol-formaldehyde resin is provided. The method includes extracting a biomass pyrolysis oil to obtain a first phenolic mixture, and polymerizing the first phenolic mixture to form a phenol-formaldehyde resin solution under an aldehyde, an alcohol and an alkaline catalyst. The disclosure also provides a resin material prepared from the phenol-formaldehyde resin. The disclosure further provides a method for preparing a resin molding material.