Patents by Inventor Min-Yong Lee
Min-Yong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7825015Abstract: The present invention provides a method for implanting ions in a semiconductor device capable of compensating for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate and another method for fabricating a semiconductor device capable of improving distribution of transistor parameters inside a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile.Type: GrantFiled: December 30, 2004Date of Patent: November 2, 2010Assignee: Hynix Semiconductor, Inc.Inventors: Yong-Sun Sohn, Seung-Woo Jin, Min-Yong Lee, Kyoung-Bong Rouh
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Patent number: 7790551Abstract: A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.Type: GrantFiled: October 22, 2009Date of Patent: September 7, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7772101Abstract: A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of preparing a semiconductor substrate having a junction area formed with a dielectric layer, forming an interlayer dielectric layer having etching selectivity lower than that of the dielectric layer over an entire structure, and forming a contact hole by removing predetermined portions of the interlayer dielectric layer and the dielectric layer. The contact area between the PN diode and the semiconductor substrate is increased so that interfacial resistance is reduced.Type: GrantFiled: June 25, 2008Date of Patent: August 10, 2010Assignee: Hynix Semiconductor Inc.Inventors: Su-Jin Chae, Keum-Bum Lee, Min-Yong Lee
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Publication number: 20100099244Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.Type: ApplicationFiled: December 23, 2009Publication date: April 22, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyoung Bong Rouh, Yong Sun Sohn, Min Yong Lee
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Patent number: 7700442Abstract: A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern disposed on the semiconductor substrate, a gate stack disposed on the semiconductor such that the gate stack protrudes from the surface of the semiconductor substrate while the gate stack fills the trench, and first and second dopant regions disposed at the upper part of the semiconductor substrate adjacent to the first and second sidewalls of the trench, respectively, such that the first and second dopant regions have different steps.Type: GrantFiled: December 21, 2007Date of Patent: April 20, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee
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Patent number: 7687350Abstract: A method for manufacturing a semiconductor memory device using asymmetric junction ion implantation, including performing ion implantation for adjusting a threshold voltage to a semiconductor substrate, forming a gate stack on the semiconductor substrate to define a storage node junction region and a bit line junction region, implanting a first conductive impurity ion and a second conductive impurity ion using a mask layer pattern covering the storage node junction region while exposing the bit line junction region, forming a gate spacer layer at both sides of the gate stack, and implanting the first conductive impurity ion using the gate stack and the gate spacer layer as an ion implantation mask layer to form a storage node junction region and a bit line junction region having different impurity concentrations, and different junction depths from each other.Type: GrantFiled: June 9, 2006Date of Patent: March 30, 2010Assignee: Hynix Semiconductor Inc.Inventors: Min Yong Lee, Kyoung Bong Rouh, Seung Woo Jin
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Patent number: 7687852Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.Type: GrantFiled: February 16, 2009Date of Patent: March 30, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7678653Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.Type: GrantFiled: February 16, 2009Date of Patent: March 16, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Publication number: 20100041196Abstract: A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.Type: ApplicationFiled: October 22, 2009Publication date: February 18, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7662705Abstract: Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones.Type: GrantFiled: August 4, 2005Date of Patent: February 16, 2010Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Yong Sun Sohn, Min Yong Lee
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Publication number: 20090321705Abstract: A phase change memory device includes a semiconductor substrate, a first conductive pattern formed on the semiconductor substrate, a second conductive pattern contacting an upper surface of the first conductive pattern and having a diameter less than a diameter of the first conductive pattern, and a phase change material layer contacting the second conductive pattern.Type: ApplicationFiled: October 22, 2008Publication date: December 31, 2009Applicant: Hynix Semiconductor, Inc.Inventors: Min Yong Lee, Su Jin Chae, Keum Bum Lee, Dong Ryeol Lee, Hyung Suk Lee
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Publication number: 20090256209Abstract: A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a side of the first gate conductive film, a plurality of trenches formed between the gates, a second gate oxide film formed on an interior wall of each trench; and a second conductive film formed in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film and the thermal oxide film.Type: ApplicationFiled: June 16, 2009Publication date: October 15, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Young Bog Kim, Jun Soo Chang, Min Yong Lee, Yong Seok Eun
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Patent number: 7563673Abstract: Disclosed herein is a method for forming a gate structure of a semiconductor device. The method comprises forming a plurality of gates including a first gate dielectric film, a first gate conductive film, and a gate silicide film sequentially stacked on a silicon substrate having a field oxide film, forming a thermal oxide film on a side of the first gate conductive film, etching the silicon substrate exposed between the plurality of gates to a predetermined depth to form a plurality of trenches, forming a second gate oxide film on the interior wall of the trenches, and forming a second gate conductive film in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film, and the thermal oxide film.Type: GrantFiled: November 8, 2005Date of Patent: July 21, 2009Assignee: Hynix Semiconductor Inc.Inventors: Young Bog Kim, Jun Soo Chang, Min Yong Lee, Yong Seok Eun
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Publication number: 20090173996Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.Type: ApplicationFiled: February 16, 2009Publication date: July 9, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Publication number: 20090170265Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.Type: ApplicationFiled: February 16, 2009Publication date: July 2, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7554106Abstract: An ion implantation apparatus comprises an ion beam source for generating an initial ion beam, a bundled ion beam generator adapted to change the initial ion beam into a bundled ion beam based on a predetermined frequency to pass the bundled ion beam for a first time while passing the initial ion beam for a second time, a beam line for accelerating the ion beam having passed through the ion beam generator, and an end station for arranging a wafer therein to allow the ion beam accelerated by the beam line to be implanted in the wafer, the end station operating to move the wafer in a direction perpendicular to an ion beam implantation direction, so as to implant the bundled ion beam in a first region of the wafer and the initial ion beam in a second region of the wafer.Type: GrantFiled: June 1, 2006Date of Patent: June 30, 2009Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Patent number: 7538003Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor comprises forming a source region of a first conductivity type and a drain region of the first conductivity type, which are separated from each other by a channel region, in upper regions of a semiconductor substrate, forming a gate stack on the channel region, and feeding hydrogen into junctions of the source and drain regions to neutralize dopants of the first conductivity type present within particular portions of the junctions.Type: GrantFiled: December 28, 2006Date of Patent: May 26, 2009Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Min Yong Lee, Yong Soo Joung
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Patent number: 7529116Abstract: Disclosed herein is a memory device having an increased level of integration with a simplified method of manufacture.Type: GrantFiled: June 29, 2007Date of Patent: May 5, 2009Assignee: Hynix Semiconductor Inc.Inventors: Yong Soo Jung, Min Yong Lee
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Patent number: 7511337Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.Type: GrantFiled: August 10, 2006Date of Patent: March 31, 2009Assignee: Hynix Semiconductor Inc.Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Yong Lee, Yong Soo Jung
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Publication number: 20090045389Abstract: A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.Type: ApplicationFiled: July 8, 2008Publication date: February 19, 2009Applicant: HYNIX SEMICONDUCTOR, INC.Inventors: Yong Seok Eun, Su Jin Chae, Keum Bum Lee, Heon Yong Chang, Min Yong Lee