Abstract: The present disclosure relates to a power amplifier circuit. The power amplifier circuit includes a voltage-controlled current source and a current mirror. The voltage-controlled current source is configured to receive a first voltage and to generate a first current. The current mirror is connected to the voltage-controlled current source and to generate a second current in response to the first current. The second current continuously changes from 0 mA to about 120 mA as the first voltage continuously changes from 0 V to about 1 V.

Abstract: The present disclosure relates to a logic control circuit including a first inverter and a voltage limiter. The first inverter is connected to a first input voltage. The first inverter includes a first transistor having a first terminal and a second terminal. The second terminal of the first transistor is connected to a ground. The voltage limiter includes a second transistor. The second transistor has a gate connected to a ground, a source connected to the first terminal of the first transistor and a drain connected to a second input voltage.

Abstract: The present disclosure describes how a master beacon having a known QUID can be used to capture beacons within its range and superimpose a systematic address scheme on those beacons. The superimposed address scheme can then be used as a proxy for the individual beacons when developing applications that make use of the beacons. A master beacon automatically detects each beacon in a plurality of beacons and, for a set of beacons in the plurality of beacons, automatically changes either the first profile identifier or the second profile identifier for each beacon in the set of beacons. The change is such that the first profile identifier or the second profile identifier is identical for each beacon in the set of beacons and is also associated with the master beacon.

Abstract: A call setup method and associated apparatus discloses sending a first message to a network device, wherein the first message is used by the electronic device to request to set up an outgoing call; receiving a second message sent by the network device, wherein the second message is used by the electronic device to set up an incoming call; caching the second message when the electronic device is in a call initiation state; releasing the outgoing call based on an indication message received from the network device and setting up the incoming call.

Abstract: The present disclosure describes systems and methods to provide a digital wakeup timer with reduced size and lower power. An example system or apparatus includes a wakeup timer employing a digital-intensive frequency-locked loop (DFLL) architecture to fully utilize the advantages of advanced CMOS processes. Such a system includes a bang-bang frequency detector, a digital loop filter, a digitally-controlled oscillator (DCO), and a multi-phase clock generator. An output of the bang-bang frequency detector is provided to an input of the digital loop filter. An output of the digital loop filter is provided to the DCO. An output of the DCO includes information indicative of an output frequency. The multi-phase clock generator provides respective clock signals based on the output frequency to the bang-bang frequency detector, the digital loop filter, and the DCO.

Abstract: The present disclosure describes how a master beacon having a known UUID can be used to capture beacons within its range and superimpose a systematic address scheme on those beacons. The superimposed address scheme can then be used as a proxy for the individual beacons when developing applications that make use of the beacons. A master beacon automatically detects each beacon in a plurality of beacons and, for a set of beacons in the plurality of beacons, automatically changes either the first profile identifier or the second profile identifier for each beacon in the set of beacons. The change is such that the first profile identifier or the second profile identifier is identical for each beacon in the set of beacons and is also associated with the master beacon.

Abstract: The present disclosure describes systems and methods to provide a digital wakeup timer with reduced size and lower power. An example system or apparatus includes a wakeup timer employing a digital-intensive frequency-locked loop (DFLL) architecture to fully utilize the advantages of advanced CMOS processes. Such a system includes a bang-bang frequency detector, a digital loop filter, a digitally-controlled oscillator (DCO), and a multi-phase clock generator. An output of the bang-bang frequency detector is provided to an input of the digital loop filter. An output of the digital loop filter is provided to the DCO. An output of the DCO includes information indicative of an output frequency. The multi-phase clock generator provides respective clock signals based on the output frequency to the bang-bang frequency detector, the digital loop filter, and the DCO.

Abstract: Embodiments of present invention provide various device assemblies for digital communication. The device assemblies may include a main printed-circuit-board (PCB); and an OSA-on-daughter-board (OODB) directly connected to the main PCB. The OODB has an optical sub-assembly (OSA) wire-bonded onto a daughter PCB. In one embodiment, the daughter PCB includes a flexible printed-circuit (FPC) sheet connecting the OODB directly to the main PCB. In another embodiment, the main PCB includes a FPC sheet connecting the main PCB directly to the OODB. In one embodiment, the connection may be made through an anisotropic conductive film or an anisotropic conductive adhesive.

Abstract: The present disclosure relates to a power amplifier circuit including a current source, a power control circuit, a current mirror and an output circuit. The current source circuit includes a first transistor and a second transistor. A source of the first transistor is connected to a drain of the second transistor and a gate of the first transistor is connected to a source with the second transistor. The power control circuit is connected to a gate of the second transistor. The current mirror circuit is connected to the gate of the first transistor and a source of the second transistor. The output circuit is connected to the current mirror circuit.

Abstract: The present disclosure relates to a logic control circuit including a first inverter and a voltage limiter. The first inverter is connected to a first input voltage. The first inverter includes a first transistor having a first terminal and a second terminal. The second terminal of the first transistor is connected to a ground. The voltage limiter includes a second transistor. The second transistor has a gate connected to a ground, a source connected to the first terminal of the first transistor and a drain connected to a second input voltage.

Abstract: A Channel State Information (CSI) feedback method and a User Equipment (UE) are disclosed. The method comprises the following steps of: determining a set of coordinated Base Stations (BSs) participating multi-BS coordination, the set of coordination BSs containing a serving BS and at least one non-serving BS; for each BS in the set of coordinated BSs: calculating a Signal to Interference and Noise Ratio (SINR) for a channel between a UE and the BS based on a hypothetical BS coordination mode corresponding to the BS; and deriving a Channel Quality Index (CQI) corresponding to the calculated SINR and feeding back the derived CQI to the serving BS.

Abstract: A method of offset calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration bit (B*LSB; B*MSB), analyzing a bit of the digital signal (COUT) and the calibration bit (B*LSB; B*MSB), determining an indication of a presence of offset error, and calibrating the offset error. As the determination of the calibration bit (B*LSB; B*MSB) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and thus can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Abstract: The present disclosure relates to a semiconductor device package and a manufacturing method thereof. The semiconductor device package includes a carrier, at least one electronic component, a first magnetic layer and a second magnetic layer. The carrier has a top surface on which the electronic component is disposed. The first magnetic layer is disposed on the top surface of the carrier and encapsulates the electronic component. The second magnetic layer is disposed on the first magnetic layer and covers a top surface and a lateral surface of the first magnetic layer. A permeability of the first magnetic layer is less than a permeability of the second magnetic layer.

Abstract: Systems and methods providing a wakeup receiver for latency-critical applications are described herein. An example system includes a wakeup receiver communicatively coupled to a communication channel. The wakeup receiver is configured to monitor an input signal of the communication channel and down-convert the input signal to a DC signal. The system also includes an analog to digital converter (ADC) configured to digitize the DC signal and provide an ADC output. The system further includes a digital baseband (DBB) module configured to determine a received signal strength indication (RSSI) from the signal. The DBB is also configured to, for each packet, determine a respective packet length and compare the RSSI and respective packet length with a two-dimensional template. The DBB is additionally configured to, based on the comparison, determine an interrupt condition and, based on determining the interrupt condition, generate a wakeup signal.

Abstract: A semiconductor package device includes: (1) a substrate having a top surface; (2) a passive component disposed on the substrate and having a top surface; (3) an active component disposed on the substrate and having a top surface; and (4) a package body disposed on the substrate, the package body including a first portion covering the active component and the passive component, and a second portion covering the passive component, wherein a top surface of the second portion of the package body is higher than a top surface of the first portion of the package body, and the first portion and the second portion of the package body include different materials.

Abstract: A crystal oscillator circuit comprises: a crystal oscillator; and an injection frequency generating circuit, the injection frequency generating circuit being configured to sense a signal of the crystal oscillator and amplify the sensed signal, the injection frequency generating circuit being further configured to inject the amplified signal to the crystal oscillator; wherein the crystal oscillator circuit is configured such that the crystal oscillator receives the amplified signal during an initial start-up period of the crystal oscillator and stops receiving the amplified signal at an end of the initial start-up period.

Abstract: A semiconductor package device includes a substrate, a passive component, an active component and a package body. The passive component is disposed on the substrate. The active component is disposed on the substrate. The package body is disposed on the substrate. The package body includes a first portion covering the active component and the passive component, and a second portion covering the passive component. A top surface of the second portion of the package body is higher than a top surface of the first portion of the package body.

Abstract: A method of gain calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (VIN), detecting if a binary code determined from the analog input signal (VIN) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*RES) and a calibration bit (B*LSB), analyzing a least significant bit of the digital signal (COUT) and the calibration bit (B*LSB), determining an indication of a presence of gain error in the gain module, and calibrating the gain error. As the determination of the calibration bit (B*LSB) requires only one additional comparison, as compared to normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Abstract: A user equipment receives, from the base station apparatus, bit information. The bit information indicates first information indicating one or more antenna ports and second information indicating a number of layers for downlink data symbols.

Abstract: The present disclosure provides a method in a base station for Channel State Information (CSI) process configuration and an associated base station. The method comprises: setting CSI process information for a User Equipment (UE) supporting three dimensional (3D) Multiple Input Multiple Output (MIMO), the CSI process information including at least an index of a CSI Reference Signal Resource (CSI-RS-R) for a vertical direction of a 3D MIMO antenna array; and transmitting the set CSI process information to the UE. Also disclosed are a method in a UE for CSI feedback and an associated UE.