Abstract: An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, includes an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node and a LC-tank structure coupled between the VDD power rail node and the VSS power rail node and to the RF I/O pad. The LC-tank structure includes a first ESD block between the VDD power rail node and the RF I/O pad, and a second ESD block between the VSS power rail node and the RF I/O pad. At least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes.

Abstract: A noise filter circuit for an IC is provided. The noise filter circuit comprises a decoupling unit coupled to a power pad of the IC and a current amplifier circuit coupled to the decoupling unit and the power pad of the IC. The decoupling unit generates a first current in response to a transient voltage being on the power pad of the IC. The current amplifier circuit drains a second current from the power pad of the IC according to the first current.

Abstract: An ESD protection circuit has a merged triggering mechanism. The ESD protection circuit comprises: an ESD detection circuit, for detecting an ESD voltage to generate a control signal; a first type ESD protection device, for outputting a first trigger current; a second type ESD protection device, for receiving a second trigger current; and a trigger circuit, for constituting a conductive path according to the control signal, such that the trigger circuit can receive the first trigger current from the first type ESD protection device and outputs the second trigger current to the second type ESD protection device.

Abstract: A charge pump circuit includes at least one stage between an input end and an output end. The at least one stage includes a first CMOS transistor coupled with a first capacitor and a second CMOS transistor coupled with a second capacitor. The at least one stage is capable of receiving a first timing signal and a second timing signal for pumping an input voltage at the input end to an output voltage at the output end. During a transitional period of the first timing signal and the second timing signal, the at least one stage is capable of substantially turning off at least one of the first CMOS transistor and the second CMOS transistor for substantially reducing leakage currents flowing through at least one of the first CMOS transistor and the second CMOS transistor.

Abstract: A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier; an ESD detection circuit that triggers the SCR responsive to detect an electrostatic discharge on an ESD bus; and an ESD clamp circuit that is coupled to the first voltage line.

Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

Abstract: Gamma voltage conversion device includes a gamma voltage conversion circuit, an amplifier, and a gamma voltage adjusting circuit. The gamma voltage conversion circuit generates a first gamma voltage conformed to a first gamma curve according to a grey level. The amplifier includes a first input end receiving the first gamma voltage, a second end, and an output end. The amplifier outputs the first or a second gamma voltage conformed to a second gamma curve according to the grey level according to the first and the second ends of the amplifier. The gamma voltage adjusting circuit coupled between the second input end and the output end of the amplifier controls the amplifier to output the first or the second gamma voltage as the gamma driving voltage according to the grey level and a gamma curve selection signal.

Abstract: A corner detector comprises a PMOS threshold voltage detector and an NMOS threshold voltage detector, the PMOS threshold voltage detector is composed of a first clock terminal, a first CMOS inverter, a first capacitor, a PMOS threshold voltage function generator and a first voltage output terminal, wherein the PMOS threshold voltage function generator is electrically connected to the first capacitor and applied to generate a first formula of voltage signal as a function of threshold voltage, the NMOS threshold voltage detector is composed of a second clock terminal, a second CMOS inverter, a second capacitor, an NMOS threshold voltage function generator and a second voltage output terminal, wherein the NMOS threshold voltage function generator is electrically connected to the second capacitor and applied to generate a second formula of voltage signal as a function of threshold voltage.

Abstract: An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, includes an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node and a LC-tank structure coupled between the VDD power rail node and the VSS power rail node and to the RF I/O pad. The LC-tank structure includes a first ESD block between the VDD power rail node and the RF I/O pad, and a second ESD block between the VSS power rail node and the RF I/O pad. At least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes.

Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.

Abstract: A charge pump circuit includes at least one stage between an input end and an output end. The at least one stage includes a first CMOS transistor coupled with a first capacitor and a second CMOS transistor coupled with a second capacitor. The at least one stage is capable of receiving a first timing signal and a second timing signal for pumping an input voltage at the input end to an output voltage at the output end. During a transitional period of the first timing signal and the second timing signal, the at least one stage is capable of substantially turning off at least one of the first CMOS transistor and the second CMOS transistor for substantially reducing leakage currents flowing through at least one of the first CMOS transistor and the second CMOS transistor.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: A bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from the bird's beak effect of a field oxide layer, which results in crystalline defects, a concentrated current and a higher magnetic field and then causes abnormal operation of a rectifier. Thereby, the present invention can also reduce signal loss.

Abstract: A high-voltage NMOS transistor for ESD protection is coupled between a high-voltage I/O pad and a low-voltage terminal, and has a parasitic component between its source and drain. A trigger has an input coupled to the high-voltage I/O pad and an output coupled to the parasitic component. When the voltage on the high-voltage I/O pad raises above a threshold value, the trigger applies a voltage to trigger the parasitic component, so as to release an ESD current from the high-voltage I/O pad to the low-voltage terminal through the high-voltage NMOS transistor.

Abstract: A pixel circuit includes a pixel unit and a memory circuit. The memory circuit includes a first switch, a switch unit, a second switch, and a plurality of memory units. Each of the memory units includes a third switch and a capacitor, where the capacitors of the memory units have a same capacitance. A data accessing method applied on the pixel circuit includes determining an order of writing a plurality of first voltages, which are loaded from a data line, according to weights of bits within a first bit string, where the bits are respectively corresponding to the first voltages, and includes determining an order and loading durations of loading a plurality of second voltages, which are previously stored in the memory units, according to weights of bits within a second bit string, where the bits are respectively corresponding to the second voltages.

Abstract: The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: A corner detector comprises a PMOS threshold voltage detector and an NMOS threshold voltage detector, the PMOS threshold voltage detector is composed of a first clock terminal, a first CMOS inverter, a first capacitor, a PMOS threshold voltage function generator and a first voltage output terminal, wherein the PMOS threshold voltage function generator is electrically connected to the first capacitor and applied to generate a first formula of voltage signal as a function of threshold voltage, the NMOS threshold voltage detector is composed of a second clock terminal, a second CMOS inverter, a second capacitor, an NMOS threshold voltage function generator and a second voltage output terminal, wherein the NMOS threshold voltage function generator is electrically connected to the second capacitor and applied to generate a second formula of voltage signal as a function of threshold voltage.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.