Patents by Inventor Ming-Hsiang Song
Ming-Hsiang Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160329405Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a substrate; a gate electrode layer over the insulation region comprising a gate middle line; a first contact structure over the insulation region adjacent to the gate electrode layer comprising a first middle line, wherein the first middle line and the gate middle line has a first distance; and a second contact structure over the insulation region on a side of the gate electrode layer opposite to the first contact structure comprising a second middle line, wherein the second middle line and the gate middle line has a second distance greater than the first distance.Type: ApplicationFiled: July 18, 2016Publication date: November 10, 2016Inventors: Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Kuo-Nan Yang, Ming-Hsiang Song, Ta-Pen Guo
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Patent number: 9466978Abstract: A circuit, a multiple power domain circuit, and a method are disclosed. An embodiment is a circuit including an input circuit having a first output and a second output, the input circuit being coupled to a first power supply voltage, and a level-shifting circuit having a first input coupled to the first output of the input circuit and a second input coupled to the second output of the input circuit, the level-shifting circuit being coupled to a second power supply voltage. The circuit further includes a first transistor coupled between a first node of the level-shifting circuit and the second power supply voltage, and a control circuit having an output coupled to a gate of the first transistor, the control circuit being coupled to the second power supply voltage.Type: GrantFiled: September 19, 2013Date of Patent: October 11, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hui Chen, Chia-Hung Chu, Kuo-Ji Chen, Ming-Hsiang Song, Lee-Chung Lu
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Patent number: 9443840Abstract: Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type.Type: GrantFiled: December 3, 2014Date of Patent: September 13, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ying Hsu, Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song, Johannes Van Zwol, Taede Smedes
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Patent number: 9443850Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between two gate devices. The device further includes at least one dummy gate between two epitaxially grown active regions. Each active region is substantially uniform in length.Type: GrantFiled: July 1, 2013Date of Patent: September 13, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wun-Jie Lin, Jen-Chou Tseng, Ming-Hsiang Song
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Patent number: 9425247Abstract: A metal insulator metal (MIM) capacitor includes a top electrode, a first via contacting a first surface of the top electrode, a bottom electrode, a second via contacting a second surface of the bottom electrode, and an insulator between the top electrode and the bottom electrode. One of the top and the bottom electrodes includes a first part and a second part. The first part has a first edge and a second edge opposing the first edge. The second part shares the second edge with the first part. At least a portion of the first edge contacts the respective via, and a first one of the first and the second edges is longer than a second one of the first and the second edges.Type: GrantFiled: November 2, 2015Date of Patent: August 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Jong Wang, Huey-Chi Chu, Kuo-Ji Chen, Ming-Hsiang Song, Wen-Chuan Chiang
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Publication number: 20160211169Abstract: A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.Type: ApplicationFiled: March 18, 2016Publication date: July 21, 2016Inventors: Sun-Jay Chang, Ming-Hsiang Song, Jen-Chou Tseng, Wun-Jie Lin, Bo-Ting Chen
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Patent number: 9397217Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a substrate; a gate electrode layer over the insulation region comprising a gate middle line; a first contact structure over the insulation region adjacent to the gate electrode layer comprising a first middle line, wherein the first middle line and the gate middle line has a first distance; and a second contact structure over the insulation region on a side of the gate electrode layer opposite to the first contact structure comprising a second middle line, wherein the second middle line and the gate middle line has a second distance greater than the first distance.Type: GrantFiled: December 28, 2012Date of Patent: July 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Jen Tseng, Ting-Wei Chang, Wei-Yu Chen, Kuo-Nan Yang, Ming-Hsiang Song, Ta-Pen Guo
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Publication number: 20160133619Abstract: A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.Type: ApplicationFiled: December 30, 2015Publication date: May 12, 2016Inventors: Ming-Hsiang Song, Jam-Wem Lee, Yi-Feng Chang, Wun-Jie Lin
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Publication number: 20160118462Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.Type: ApplicationFiled: January 4, 2016Publication date: April 28, 2016Inventors: Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Kuo-Nan Yang, Ming-Hsiang Song, Ta-Pen Guo
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Patent number: 9318621Abstract: A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode.Type: GrantFiled: March 8, 2013Date of Patent: April 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sun-Jay Chang, Ming-Hsiang Song, Jen-Chou Tseng, Wun-Jie Lin, Bo-Ting Chen
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Publication number: 20160071920Abstract: A metal insulator metal (MIM) capacitor includes a top electrode, a first via contacting a first surface of the top electrode, a bottom electrode, a second via contacting a second surface of the bottom electrode, and an insulator between the top electrode and the bottom electrode. One of the top and the bottom electrodes includes a first part and a second part. The first part has a first edge and a second edge opposing the first edge. The second part shares the second edge with the first part. At least a portion of the first edge contacts the respective via, and a first one of the first and the second edges is longer than a second one of the first and the second edges.Type: ApplicationFiled: November 2, 2015Publication date: March 10, 2016Inventors: Chen-Jong Wang, Huey-Chi Chu, Kuo-Ji Chen, Ming-Hsiang Song, Wen-Chuan Chiang
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Publication number: 20160043545Abstract: The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, and an ESD detection circuit coupled to the common trigger line and to a first power line common to the other dies, wherein when the ESD detection circuit of one of the plural dies detects an ESD event, the ESD detection circuit is configured to generate a control signal to the common trigger line to control a power clamp in each of the plural dies to clamp an ESD event to the common first power line or a second power line.Type: ApplicationFiled: October 23, 2015Publication date: February 11, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzu-Heng CHANG, Jen-Chou TSENG, Ming-Hsiang SONG
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Patent number: 9245878Abstract: An ESD protection circuit includes at least a first and a second silicon controlled rectifier (SCR) circuits. The first SCR circuit is coupled between the pad and the positive power supply terminal. The second SCR circuit is coupled between the pad and the ground terminal. At least one of the SCR circuits is configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal.Type: GrantFiled: April 14, 2014Date of Patent: January 26, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Hsiang Song, Jam-Wem Lee, Tzu-Heng Chang, Yu-Ying Hsu
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Patent number: 9231106Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.Type: GrantFiled: March 8, 2013Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Jen Tseng, Ting-Wei Chiang, Wei-Yu Chen, Kuo-Nan Yang, Ming-Hsiang Song, Ta-Pen Guo
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Patent number: 9230961Abstract: A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.Type: GrantFiled: November 14, 2013Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming-Hsiang Song, Jam-Wem Lee, Yi-Feng Chang, Wun-Jie Hung Lin
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Publication number: 20150380396Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.Type: ApplicationFiled: September 3, 2015Publication date: December 31, 2015Inventors: Yu-Ti Su, Wun-Jie Lin, Han-Jen Yang, Shui-Ming Cheng, Ming-Hsiang Song
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Patent number: 9178008Abstract: Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.Type: GrantFiled: August 10, 2012Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ji Chen, Wen-Chuan Chiang, Huey-Chi Chu, Ming-Hsiang Song, Chen-Jong Wang
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Publication number: 20150311192Abstract: A method comprises forming an active region including a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by an isolation region, depositing an epitaxial growth block layer over the active region, patterning the epitaxial growth block layer to define a first growth area and a second growth area and growing an N+ region in the first growth area and a P+ region in the second growth area.Type: ApplicationFiled: July 10, 2015Publication date: October 29, 2015Inventors: Wun-Jie Lin, Bo-Ting Chen, Jen-Chou Tseng, Ming-Hsiang Song
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Patent number: 9172242Abstract: The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, the trigger line controlling the power of a power clamp in each respective die, a dedicated electrostatic discharge (ESD) line for each respective die, and an ESD detection circuit connected to the dedicated ESD line and to a first power line common to the other dies. When an input signal is received by the ESD detection circuit of one of the plural dies, the ESD detection circuit generates an output signal to the common trigger line to supply power to the power clamp in each of the plural dies to clamp ESD voltage or current to the common first power line or a second power line.Type: GrantFiled: November 2, 2012Date of Patent: October 27, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song
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Patent number: 9147676Abstract: An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.Type: GrantFiled: October 2, 2013Date of Patent: September 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ti Su, Wun-Jie Lin, Han-Jen Yang, Shui-Ming Cheng, Ming-Hsiang Song