Abstract: Method for forming semiconductor device structure includes forming a sacrificial layer between first and second stacks of layers, the first stack of layers comprises first and second semiconductor layers alternatingly stacked, and the second stack of layers comprises third and fourth semiconductor layers alternatingly stacked, wherein the sacrificial layer comprises a semiconductor metal oxide, forming a sacrificial gate structure over portion of the second stack of layers, removing portions of the first and second stack of layers not covered by the sacrificial gate structure, removing the sacrificial layer to form cavity, filling the cavity with a dielectric to form an isolation layer, and forming first and second source/drain features on opposing sides of sacrificial gate structure, wherein the first source/drain feature is disposed below the second source/drain feature, and the first and second source/drain features are in contact with the isolation layer, first semiconductor layers, and third semiconducto

Abstract: The present disclosure describes a semiconductor device having a source/drain structure with a dopant cluster. The semiconductor device includes a channel structure on a substrate and a source/drain structure on the substrate and adjacent to the channel structure. The source/drain structure includes a first epitaxial layer on the substrate, a second epitaxial layer on the first epitaxial layer and sidewalls of the channel structure, and a third epitaxial layer on the second epitaxial layer. The second epitaxial layer includes a cluster of a dopant extending along a direction of the channel structure.

Abstract: A method includes forming a fin protruding from a substrate; forming an isolation region surrounding the fin; forming a gate structure extending over the fin and the isolation region; etching the fin adjacent the gate structure to form a recess; forming a source/drain region in the recess, including performing a first epitaxial process to grow a first semiconductor material in the recess, wherein the first epitaxial process preferentially forms facet planes of a first crystalline orientation; and performing a second epitaxial process to grow a second semiconductor material on the first semiconductor material, wherein the second epitaxial process preferentially forms facet planes of a second crystalline orientation, wherein a top surface of the second semiconductor material is above a top surface of the fin; and forming a source/drain contact on the source/drain region.

Abstract: A semiconductor device and the method of forming the same are provided. The semiconductor device may comprise a first plurality of nanostructures, a second plurality of nanostructures over a substrate, a first gate stack extending between the nanostructures of the first plurality of nanostructures, a second gate stack extending between the nanostructures of the second plurality of nanostructures, a first source/drain region in contact with a first nanostructure of the first plurality of nanostructures, a second source/drain region in contact with a first nanostructure of the second plurality of nanostructures, wherein the second source/drain region may be separated from the first source/drain region, a silicide layer between the first source/drain region and the second source/drain region, and an isolation layer between the silicide layer and the substrate.

Abstract: Embodiments with present disclosure provides a gate-all-around FET device including extended bottom inner spacers. The extended bottom inner prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second nanostructured channel regions disposed on the substrate, a gate structure surrounding the first and second nanostructured channel regions, an inner gate spacer disposed along a sidewall of the gate structure and between the first and second nanostructured channel regions, and a source/drain (S/D) region. The S/D region includes an epitaxial liner disposed along sidewalls of the first and second nanostructured channel regions and the inner gate spacer and a germanium-based epitaxial region disposed on the epitaxial liner. The semiconductor further includes an isolation structure disposed between the germanium-based epitaxial region and the substrate.

Abstract: Embodiments with present disclosure provides a gate-all-around FET device including a patterned or lowered bottom dielectric layer. The bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

Abstract: A method includes forming a plurality of semiconductor regions on a wafer, placing the wafer in an etching chamber, globally heating the wafer using a heating source, and projecting a laser beam on the wafer. When the wafer is heated by both of the heating source and the laser beam, the plurality of semiconductor regions on the wafer are etched.

Abstract: Embodiments of the present disclosure provide a furnace for semiconductor processing that includes an inner tube defining a reaction chamber and including a sidewall defined along a longitudinal axis of the inner tube and including one or more slits defined through the sidewall in a radial direction with respect to the longitudinal axis. The one or more slits include at least one of a first slit with a width in a range between 10 mm and 100 mm, or a plurality of separate slits with a total number in a range between 2 and 15. The inner tube includes a closed end substantially enclosing the reaction chamber and an open end opposite the closed end with respect to the longitudinal axis. The reaction chamber is configured to be loaded with one or more semiconductor wafers via the open end.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming a stack over a substrate, forming a fin-shape structure from patterning the stack and the substrate, recessing the fin-shape structure to form a source/drain trench, depositing a dielectric film in the source/drain trench with a top surface below a top surface of the substrate in the fin-shape structure, and forming an epitaxial feature over the dielectric film. A bottom surface of the epitaxial feature is below the top surface of the substrate in the fin-shape structure.

Abstract: A method includes forming a fin protruding from a substrate; forming an isolation region surrounding the fin; forming a gate structure extending over the fin and the isolation region; etching the fin adjacent the gate structure to form a recess; forming a source/drain region in the recess, including performing a first epitaxial process to grow a first semiconductor material in the recess, wherein the first epitaxial process preferentially forms facet planes of a first crystalline orientation; and performing a second epitaxial process to grow a second semiconductor material on the first semiconductor material, wherein the second epitaxial process preferentially forms facet planes of a second crystalline orientation, wherein a top surface of the second semiconductor material is above a top surface of the fin; and forming a source/drain contact on the source/drain region.

Abstract: A device includes a semiconductor channel region over a substrate, a shallow trench isolation (STI) region in the substrate, a gate structure over the semiconductor channel region. The semiconductor channel region has a channel top higher than a top surface of the STI region by a first height. The device further includes a first source/drain epitaxy structure and a second source/drain epitaxy structure respectively at opposite sides of the gate structure, and a first dielectric fin sidewall structure and a second dielectric fin sidewall structure on opposite sides of the first source/drain epitaxy structure, respectively. A top of the first dielectric fin sidewall structure is higher than the top surface of the STI region by a second height. The second height is at most half the first height.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

Abstract: In an embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes and a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer having a first dopant concentration of boron. The device also includes and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed in a recess between two adjacent channel regions, wherein the S/D feature comprises an epitaxial layer conformally deposited on an exposed surface of the recess. The structure also includes a silicide layer conformally disposed on the S/D feature, and a S/D contact disposed on the silicide layer, wherein the S/D contact has a first portion extending into the recess, and the first portion has at least three surfaces being surrounded by the silicide layer and the S/D feature.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: In an embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes and a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer having a first dopant concentration of boron. The device also includes and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration.

Abstract: A fin field effect transistor (Fin FET) device includes fin structure extending in first direction and protruding from isolation insulating layer disposed over substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.