Abstract: A method of forming a semiconductor device includes depositing a p-type semiconductor layer over a portion of a semiconductor substrate, depositing a semiconductor layer over the p-type semiconductor layer, wherein the semiconductor layer is free from p-type impurities, forming a gate stack directly over a first portion of the semiconductor layer, and etching a second portion of the semiconductor layer to form a trench extending into the semiconductor layer. At least a surface of the p-type semiconductor layer is exposed to the trench. A source/drain region is formed in the trench. The source/drain region is of n-type.

Abstract: Embodiments of the present disclosure relate to a semiconductor device with lowered source/drain regions to reduce channel resistance (Rch) and source/drain contact resistance loading.

Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: Methods of forming a low-resistance source/drain feature for a multi-gate device are provided. A example method includes forming a fin-shaped structure that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, recessing a source/drain region of the fin-shaped structure to form a source/drain recess, selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, forming a bottom dielectric layer over the substrate, depositing a first epitaxial layer over the inner spacers and the sidewalls of the plurality of the channel layers, performing a thermal treatment to reshape the first epitaxial layer, after the performing of the thermal treatment, depositing a second epitaxial layer over the first epitaxial layer. The first epitaxial layer includes germanium and the second epitaxial layer is free of germanium.

Abstract: The present disclosure describes a semiconductor device having a source/drain (S/D) structure with a void. The semiconductor device includes a stack of semiconductor layers on a substrate, a gate structure surrounding the stack of semiconductor layers, and a S/D structure on the substrate and in contact with the stack of semiconductor layers. The S/D structure includes a void below a top surface of the S/D structure.

Abstract: A semiconductor device includes a substrate, first and second fins over the substrate and extending upwardly in a first direction, an epitaxial material comprising a first portion, a second portion, and a third portion, and a conductive feature in contact with the epitaxial material. The first portion is located on the first fin, the second portion is located on the second fin, and the third portion is connected to the first and second portions. The third portion has a bottom surface bended upwardly with an apex located between the first and second fins. In a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins, the bottom surface has a first straight line and a second straight line intersecting at the apex.

Abstract: A semiconductor device includes a substrate. Semiconductor layers are stacked one above another over the substrate. A gate structure wraps around each of the semiconductor layers. Epitaxial layers are over the substrate and in contact with opposite ends of a bottommost one of the semiconductor layers. Source/drain epitaxial structures are over and in contact with the epitaxial layers, respectively. Dielectric structures vertically between the epitaxial layers and the respective source/drain epitaxial structures, respectively.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes etching a source/drain recess in a semiconductor substrate and performing an epitaxy process to form a source/drain epitaxial structure in the source/drain recess. The epitaxy process comprises a plurality of cycles, each of the cycles comprises depositing a semiconductor material by introducing a plasma-phase precursor and a gas-phase precursor to the semiconductor substrate.

Abstract: A method includes forming a plurality of semiconductor regions on a wafer, placing the wafer in an etching chamber, globally heating the wafer using a heating source, and projecting a laser beam on the wafer. When the wafer is heated by both of the heating source and the laser beam, the plurality of semiconductor regions on the wafer are etched.

Abstract: Method for forming semiconductor device structure includes forming a sacrificial layer between first and second stacks of layers, the first stack of layers comprises first and second semiconductor layers alternatingly stacked, and the second stack of layers comprises third and fourth semiconductor layers alternatingly stacked, wherein the sacrificial layer comprises a semiconductor metal oxide, forming a sacrificial gate structure over portion of the second stack of layers, removing portions of the first and second stack of layers not covered by the sacrificial gate structure, removing the sacrificial layer to form cavity, filling the cavity with a dielectric to form an isolation layer, and forming first and second source/drain features on opposing sides of sacrificial gate structure, wherein the first source/drain feature is disposed below the second source/drain feature, and the first and second source/drain features are in contact with the isolation layer, first semiconductor layers, and third semiconducto

Abstract: The present disclosure describes a semiconductor device having a source/drain structure with a dopant cluster. The semiconductor device includes a channel structure on a substrate and a source/drain structure on the substrate and adjacent to the channel structure. The source/drain structure includes a first epitaxial layer on the substrate, a second epitaxial layer on the first epitaxial layer and sidewalls of the channel structure, and a third epitaxial layer on the second epitaxial layer. The second epitaxial layer includes a cluster of a dopant extending along a direction of the channel structure.

Abstract: A method includes forming a fin protruding from a substrate; forming an isolation region surrounding the fin; forming a gate structure extending over the fin and the isolation region; etching the fin adjacent the gate structure to form a recess; forming a source/drain region in the recess, including performing a first epitaxial process to grow a first semiconductor material in the recess, wherein the first epitaxial process preferentially forms facet planes of a first crystalline orientation; and performing a second epitaxial process to grow a second semiconductor material on the first semiconductor material, wherein the second epitaxial process preferentially forms facet planes of a second crystalline orientation, wherein a top surface of the second semiconductor material is above a top surface of the fin; and forming a source/drain contact on the source/drain region.

Abstract: A semiconductor device and the method of forming the same are provided. The semiconductor device may comprise a first plurality of nanostructures, a second plurality of nanostructures over a substrate, a first gate stack extending between the nanostructures of the first plurality of nanostructures, a second gate stack extending between the nanostructures of the second plurality of nanostructures, a first source/drain region in contact with a first nanostructure of the first plurality of nanostructures, a second source/drain region in contact with a first nanostructure of the second plurality of nanostructures, wherein the second source/drain region may be separated from the first source/drain region, a silicide layer between the first source/drain region and the second source/drain region, and an isolation layer between the silicide layer and the substrate.

Abstract: Embodiments with present disclosure provides a gate-all-around FET device including a patterned or lowered bottom dielectric layer. The bottom dielectric layer prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second nanostructured channel regions disposed on the substrate, a gate structure surrounding the first and second nanostructured channel regions, an inner gate spacer disposed along a sidewall of the gate structure and between the first and second nanostructured channel regions, and a source/drain (S/D) region. The S/D region includes an epitaxial liner disposed along sidewalls of the first and second nanostructured channel regions and the inner gate spacer and a germanium-based epitaxial region disposed on the epitaxial liner. The semiconductor further includes an isolation structure disposed between the germanium-based epitaxial region and the substrate.

Abstract: Embodiments with present disclosure provides a gate-all-around FET device including extended bottom inner spacers. The extended bottom inner prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.

Abstract: A method includes forming a plurality of semiconductor regions on a wafer, placing the wafer in an etching chamber, globally heating the wafer using a heating source, and projecting a laser beam on the wafer. When the wafer is heated by both of the heating source and the laser beam, the plurality of semiconductor regions on the wafer are etched.

Abstract: Embodiments of the present disclosure provide a furnace for semiconductor processing that includes an inner tube defining a reaction chamber and including a sidewall defined along a longitudinal axis of the inner tube and including one or more slits defined through the sidewall in a radial direction with respect to the longitudinal axis. The one or more slits include at least one of a first slit with a width in a range between 10 mm and 100 mm, or a plurality of separate slits with a total number in a range between 2 and 15. The inner tube includes a closed end substantially enclosing the reaction chamber and an open end opposite the closed end with respect to the longitudinal axis. The reaction chamber is configured to be loaded with one or more semiconductor wafers via the open end.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming a stack over a substrate, forming a fin-shape structure from patterning the stack and the substrate, recessing the fin-shape structure to form a source/drain trench, depositing a dielectric film in the source/drain trench with a top surface below a top surface of the substrate in the fin-shape structure, and forming an epitaxial feature over the dielectric film. A bottom surface of the epitaxial feature is below the top surface of the substrate in the fin-shape structure.