Abstract: A circuit includes a memory array including memory cells; and input/output (I/O) circuits, each of the I/O circuits including a corresponding sense amplifier that is operatively coupled to a corresponding subset of the memory cells. Each of the I/O circuits includes a first input level shifter, a second input level shifter, and an output level shifter, each of the first input level shifter, the second input level shifter, and the output level shifter being coupled between a first voltage domain and a second voltage domain. The output level shifter has an input directly coupled to an output of a first multiplexer, the first multiplexer operating in the second voltage domain and configured to select one of a first signal present on a first input of the first multiplexer or a second signal present on a second input of the first multiplexer based on a first control signal.

Abstract: An air-pulse generating device comprises a film structure comprising a flap pair, wherein the flap pair comprises a first flap and a second flap opposite to each other; wherein the flap pair operates at an ultrasonic frequency, such that the air-pulse generating device produces a plurality of air pulses at an ultrasonic pulse rate; wherein the flap pair possesses an initial deflection difference or exhibits an average displacement difference between the first flap and the second flap; wherein during a first phase, the first flap initially deflects toward a first direction; wherein during a second phase, the second flap initially deflects toward the first direction.

Abstract: A circuit includes a memory array comprising nominal memory cells and at least a tracking memory cell, the tracking memory cell coupled to a tracking bit line and a tracking word line; a comparator configured to compare a reference voltage with a varying supply voltage to determine a logic state of a mode selection signal; and a controller. The controller can, in response to a first logic state of the mode selection signal, provide a first signal on the tracking word line and provide a second signal to reset the first signal based on a third signal present along a first discharging path; and, in response to a second logic state of the mode selection signal, provide the first signal on the tracking word line and provide the second signal based on a fourth signal configured to form a second discharging path.

Abstract: A driving circuit includes a valve driving signal generator, configured to generate a first valve driving signal and a second valve driving signal. The driving circuit is configured to drive an air-pulse generating device. The air-pulse generating device includes a flap pair. The flap pair includes a first flap and a second flap. The flap pair is driven by the valve driving signal generator to possess an initial deflection difference or exhibits an average displacement difference between the first flap and the second flap.

Abstract: Memory systems, devices, and a method of operating the same are disclosed. In one aspect, a system includes a first memory device. The first memory device includes a first memory element, a first input port, and a first internal scan chain coupled between the first memory element and the first input port. The system includes a second memory device. The second memory device includes a second memory element, a second input port, and a second internal scan chain coupled between the second memory element and the second input port. The system includes a control circuit configured to propagate a first test vector through the first internal scan chain and a second test vector through the second internal scan chain.

Abstract: A semiconductor device includes a bit line pre-charger and a buffer circuit. The bit line pre-charger is configured to charge at least one bit line when a first control signal has a first voltage level. The buffer circuit is configured to generate the first control signal. During a first standby period, the buffer circuit adjusts the first control signal to a second voltage level different from the first voltage level.

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.

Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.

Abstract: A memory device is provided and includes a memory array, first to second latch circuits and a gating circuit. Read and write operations are triggered by first and second edges of an internal clock signal respectively. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal generated based on the first edge of the internal clock signal. The second latch circuit generates a second output signal in response to the first output signal and a second latch clock signal, a first edge of the second latch clock signal being between first and second edges of the first latch clock signal. The gating circuit generates, in response to the second output signal and a gating clock generated, a third output signal to the memory array.

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device.

Abstract: A memory circuit includes a memory array including memory cells, wherein each of memory cells is accessible through a plurality of access lines. The memory circuit includes a delay circuit configured to receive a first clock pulse and delay the first clock pulse as a second clock pulse, wherein the second clock pulse immediately follows the first clock pulse. The memory circuit includes a logic gate configured to receive the first clock pulse and the second clock pulse, and provide a pre-charge signal for pre-charging the plurality of access lines based on the first and second clock pulses. The delay circuit includes a plurality of inverters and a plurality of transistors, such that a time difference between a first transition edge of the first clock pulse and a second transition edge of the second clock pulse is extended in accordance with an increasing age of the memory circuit.

Abstract: A circuit includes an array including a plurality of memory cells; a driver operatively coupled to the array and configured to provide an access signal controlling an access to one or more of the plurality of memory cells; and a timing controller operatively coupled to the driver. The timing controller is configured to: receive a control signal; and in response to the control signal transitioning from a first logic state to a second logic state, adjust a pulse width of the access signal within a single clock cycle containing a first phase and a second phase, wherein the first phase includes reading a first data bit stored in a first one of the one or more memory cells and the second phase includes writing a second data bit into the first memory cell.

Abstract: A memory device is provided and includes a memory array, first to second latch circuits and a gating circuit. Read and write operations are triggered by first and second edges of an internal clock signal respectively. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal generated based on the first edge of the internal clock signal. The second latch circuit generates a second output signal in response to the first output signal and a second latch clock signal, a first edge of the second latch clock signal being between first and second edges of the first latch clock signal. The gating circuit generates, in response to the second output signal and a gating clock generated, a third output signal to the memory array.

Abstract: A circuit includes an array including a plurality of memory cells; a driver operatively coupled to the array and configured to provide an access signal controlling an access to one or more of the plurality of memory cells; and a timing controller operatively coupled to the driver. The timing controller is configured to: receive a control signal; and in response to the control signal transitioning from a first logic state to a second logic state, adjust a pulse width of the access signal within a single clock cycle containing a first phase and a second phase, wherein the first phase includes reading a first data bit stored in a first one of the one or more memory cells and the second phase includes writing a second data bit into the first memory cell.

Abstract: A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

Abstract: A controller for controlling a sound producing device includes a vent controller and an audio amplifier. The vent controller is configured to output a first driving voltage and a second driving voltage to the sound producing device, to control the sound producing device to form a vent. The audio amplifier is configured to output a first audio signal to the sound producing device, to produce a sound. The sound producing device comprises a flap pair, and the flap pair comprises a first flap and a second flap. The vent controller outputs the first driving voltage and actuates the first flap to generate a first displacement, the vent controller outputs the second driving voltage and actuates the second flap to generate a second displacement, and the vent is formed because of a difference between the first displacement and the second displacement.

Abstract: A memory device is provided and includes a memory array, first to second latch circuits and a gating circuit. Read and write operations are triggered by first and second edges of an internal clock signal respectively. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal generated based on the first edge of the internal clock signal. The second latch circuit generates a second output signal in response to the first output signal and a second latch clock signal, a first edge of the second latch clock signal being between first and second edges of the first latch clock signal. The gating circuit generates, in response to the second output signal and a gating clock generated, a third output signal to the memory array.

Abstract: A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

Abstract: A circuit includes an array including a plurality of memory cells; a driver operatively coupled to the array and configured to provide an access signal controlling an access to one or more of the plurality of memory cells; and a timing controller operatively coupled to the driver. The timing controller is configured to: receive a control signal; and in response to the control signal transitioning from a first logic state to a second logic state, adjust a pulse width of the access signal within a single clock cycle containing a first phase and a second phase, wherein the first phase includes reading a first data bit stored in a first one of the one or more memory cells and the second phase includes writing a second data bit into the first memory cell.

Abstract: A piezoelectric valve driver device is provided. A first driver is connected to a first side of a valve. A second driver is connected to a second side of the valve. A power charging circuit is coupled between an external power source and a second voltage. A charging and discharging current controller is connected to the first driver, the second driver and the power charging circuit, and is configured to control currents of the first driver, the second driver and the power charging circuit. When a driver circuit switches the valve from a closed state to an open state, the first driver provides a first voltage to the first side of the valve, and the second voltage that is outputted to the second side of the valve by the second driver is discharged to output a discharging current to the external power source through the power charging circuit.