Abstract: The present invention discloses a dynamic power control method utilized in an amplifier. The dynamic power control method includes detecting an absolute difference between a positive supply voltage of the amplifier and an output voltage of the amplifier, to acquire a positive voltage difference; detecting an absolute difference between a negative supply voltage of the amplifier and the output voltage of the amplifier, to acquire a negative voltage difference; and adjusting the positive supply voltage and the negative supply voltage according to the positive voltage difference, the negative voltage difference and a threshold.

Abstract: An analog-to-digital converting method for converting an analog signal to a digital signal is disclosed. The analog-to-digital converting method includes decomposing the analog signal into a major analog signal and a minor analog signal, converting the major analog signal to a major digital signal, determining to which of a plurality of default sections the minor analog signal belongs to generate a minor digital signal correspondingly, and combining the major digital signal and the minor digital signal to form the digital signal.

Abstract: A pop-free single-ended output class-D amplifier includes: an input signal generator for generating an input signal; a power supply for supplying input power; a reference voltage generator for generating a reference voltage; a gain-adjustable stage for generating an amplified signal according to the reference voltage and adjusting a gain of the single-ended output class-D amplifier; a pulse width modulation module for outputting a pulse width modulation signal according to the reference voltage, the amplified signal, and the input power; a low-pass filter for low-pass filtering the pulse width modulation signal to generate an output voltage; and a logic controller for generating at least one control signal to control the reference voltage generator, the gain-adjustable stage, and the pulse width modulation module according to the input power, the reference voltage, and the pulse width modulation signal.

Abstract: The present invention discloses a dynamic power control method utilized in an amplifier. The dynamic power control method includes detecting an absolute difference between a positive supply voltage of the amplifier and an output voltage of the amplifier, to acquire a positive voltage difference; detecting an absolute difference between a negative supply voltage of the amplifier and the output voltage of the amplifier, to acquire a negative voltage difference; and adjusting the positive supply voltage and the negative supply voltage according to the positive voltage difference, the negative voltage difference and a threshold.

Abstract: An innovative dual-port subthreshold static random access memory (SRAM) cell for sub-threshold voltage operation is disclosed. During write mode, the dual-port subthreshold SRAM cell would cut off the positive feedback loop of the inverters and utilize the reverse short-channel effect to enhance write capability. The single-ended read/write port structure further reduces power consumption of the lengthy bit line. Therefore, the dual-port subthreshold SRAM cell is a suitable for long operation in a first-in first-out memory system. Although the lower voltage reduces the stability of the memory cell, the dual-port subthreshold SRAM cell of the present invention can still stably operate.

Abstract: A method buffers clock skew by using a logical effort, and is applicable to a clock tree that stays in a strong-inversion region, a moderate-inversion region, or a weak-inversion region. The method includes establishing in the clock tree a temperature sensor and a tunable-width buffer, and establishing width and temperature comparative lists according to a logical effort equation, for the tunable-width buffer to be individually applied to the strong-inversion region, the moderate-inversion region, and the weak-inversion region; selecting one from the width and temperature comparative lists that corresponds to one of the inversion regions in which the clock tree stays, enabling the temperature sensor to sense a temperature, and searching the selected width and temperature comparative list for a width that corresponds to the temperature sensed by the temperature sensor; and enabling the tunable-width buffer to perform a width modulation process according to the searched width.

Abstract: A body biasing device for an amplifier which has a P-type differential pair and outputs an output signal at an output node according to a differential input signal pair is disclosed. The body biasing device includes a detection unit coupled to the operational amplifier for detecting a detected voltage related to the differential input signals and accordingly outputting a control signal; and a selection unit coupled to the detection unit and the operational amplifier for outputting a body bias to the P-type differential pair according to the control signal.

Abstract: A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.

Abstract: A fully on-chip temperature, process, and voltage sensor includes a voltage sensor, a process sensor and a temperature sensor. The temperature sensor includes a bias current generator, a ring oscillator, a fixed pulse generator, an AND gate, and a first counter. The bias current generator generates an output current related to temperature according to the operating voltage of chip. The ring oscillator generates an oscillation signal according to the output current. The fixed pulse generator generates a fixed pulse signal. The AND gate is connected to the ring oscillator and the fixed pulse generator for performing a logic AND operation on the oscillation signal and the fixed pulse signal, and generating a temperature sensor signal.

Abstract: An innovative dual-port subthreshold static random access memory (SRAM) cell for sub-threshold voltage operation is disclosed. During write mode, the dual-port subthreshold SRAM cell would cut off the positive feedback loop of the inverters and utilize the reverse short-channel effect to enhance write capability. The single-ended read/write port structure further reduces power consumption of the lengthy bit line. Therefore, the dual-port subthreshold SRAM cell is a suitable for long operation in a first-in first-out memory system. Although the lower voltage reduces the stability of the memory cell, the dual-port subthreshold SRAM cell of the present invention can still stably operate.

Abstract: A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.

Abstract: A programmable clock generator, which is used in dynamic-voltage-and-frequency-scaling (DVFS) operated in Sub- and Near-Threshold region. The programmable clock generator includes first pulse generating unit and a pulse multiplier. A first counter is configured to generate a first counting signal, so as to control the phase detector comparing the phase difference between a first pulse signal and a second pulse signal. A first control signal is transmitted by a control unit in accordance with a phase difference signal, and the phase of the second pulse signal is adjusted by a lock-in delay unit, so that a predetermined phase is generated between the first pulse signal and the second pulse signal. The PVT variation may be compensated by the programmable clock generator during the sub threshold region. Therefore, the period of reference clock is in the locking range of lock-in delay line.

Abstract: An apparatus and a method for sensing temperature are provided. The apparatus includes a first oscillation circuit, a pulse width generator, and a comparison circuit. The first oscillation circuit is for generating a first signal having a first frequency which is related to a to-be-sensed temperature. The pulse width generator is for generating a pulse width signal, the pulse width signal having a pulse width related to the to-be-sensed temperature. The comparison circuit is for generating an output signal indicative of the value of the to-be-sensed temperature according to the first signal and the pulse width signal.

Abstract: A method buffers clock skew by using a logical effort, and is applicable to a clock tree that stays in a strong-inversion region, a moderate-inversion region, or a weak-inversion region. The method includes establishing in the clock tree a temperature sensor and a tunable-width buffer, and establishing width and temperature comparative lists according to a logical effort equation, for the tunable-width buffer to be individually applied to the strong-inversion region, the moderate-inversion region, and the weak-inversion region; selecting one from the width and temperature comparative lists that corresponds to one of the inversion regions in which the clock tree stays, enabling the temperature sensor to sense a temperature, and searching the selected width and temperature comparative list for a width that corresponds to the temperature sensed by the temperature sensor; and enabling the tunable-width buffer to perform a width modulation process according to the searched width.

Abstract: An analog-to-digital converting method for converting an analog signal to a digital signal is disclosed. The analog-to-digital converting method includes decomposing the analog signal into a major analog signal and a minor analog signal, converting the major analog signal to a major digital signal, determining to which of a plurality of default sections the minor analog signal belongs to generate a minor digital signal correspondingly, and combining the major digital signal and the minor digital signal to form the digital signal.

Abstract: A signal amplification device for amplifying a signal according to a gain indication signal is disclosed. The signal amplification device includes a pulse width modulator for generating a pulse width modulation signal according to the gain indication signal, a counter for counting a period number of the pulse width modulation signal according to a standard clock signal, and an amplifier for amplifying the signal according to the period number.

Abstract: A pin sharing method for controlling a plurality of functions of a chip via a versatile pin of the chip is disclosed. The pin sharing method includes dividing a voltage range of the versatile pin into a plurality of sections according to the plurality of functions, and assigning the plurality of sections to correspond to a plurality of modes of the plurality of functions.

Abstract: An output driving circuit capable of reducing EMI effect includes a non-overlapping signal generation unit for generating a first non-overlapping signal and a second non-overlapping signal according to an input signal, a pre-driver for generating a first pre-driving signal and a second pre-driving signal according to the first non-overlapping signal and the second non-overlapping signal, a high-side switch, a low-side switch, and a control unit for controlling the high-side switch or the low-side switch to be switched into a weak on state to reduce load inductive current effect for a load.

Abstract: A current control circuit for controlling a bias current of a class AB operational amplifier includes: a low current source, for generating a low bias current; a high current source, for generating a high bias current, which is greater than the low bias current; and a comparing and selecting unit, coupled to an output terminal of the class AB operational amplifier, for selecting one of the low bias current and the high bias current to output as the bias current according to an output voltage of the class AB OP.

Abstract: A class AB operational amplifier includes: a first transistor, for generating a first current; a second transistor, where a second source voltage of the second transistor is equal to a first source voltage of the first transistor, for generating an output stage quiescent current; and an output stage quiescent current controller, coupled to a gate and a source of the first transistor, for controlling a first drain-to-source voltage of the first transistor to be equal to a second drain-to-source voltage of the second transistor. A ratio of the output stage quiescent current to the first current is equal to a ratio of a second W/L ratio of the second transistor to a first W/L ratio of the first transistor.