Patents by Inventor Ming-Jui Chen
Ming-Jui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154972Abstract: A method for permission management includes: generating a plurality of job roles with different permissions according to organization permission table; generating first permission structure directed graph according to the job roles; selecting one of the job roles in first permission structure directed graph as target job role; generating minimum directed spanning graph in first permission structure directed graph according to target job role; determining whether permission of each of the job roles in first permission structure directed graph matches job of each of the job roles in first permission structure directed graph; and adjusting permission and job of each of the job roles to generate second permission structure directed graph if it is determined that permission of each of the job roles in first permission structure directed graph does not match job of each of the job roles in first permission structure directed graph.Type: ApplicationFiled: December 21, 2022Publication date: May 9, 2024Inventors: Wei-Chao CHEN, Ming-Chi CHANG, Chih-Pin WEI, Chuo-Jui WU
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Publication number: 20240136420Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.Type: ApplicationFiled: December 1, 2022Publication date: April 25, 2024Applicant: AUO CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
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Patent number: 11955507Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
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Publication number: 20230317779Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng, Ming-Jui Chen
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Publication number: 20230317778Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng, Ming-Jui Chen
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Patent number: 11715759Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.Type: GrantFiled: December 11, 2020Date of Patent: August 1, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng, Ming-Jui Chen
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Publication number: 20220157933Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.Type: ApplicationFiled: December 11, 2020Publication date: May 19, 2022Inventors: Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng, Ming-Jui Chen
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Patent number: 10153034Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.Type: GrantFiled: March 3, 2017Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
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Patent number: 9905562Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.Type: GrantFiled: April 10, 2017Date of Patent: February 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry Che Jen Hu, Ming-Jui Chen, Chen-Hsien Hsu
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Patent number: 9859170Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.Type: GrantFiled: February 16, 2017Date of Patent: January 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
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Patent number: 9785046Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.Type: GrantFiled: January 21, 2015Date of Patent: October 10, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee, Jian-Yuan Ma, Yan-Chun Chen
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Patent number: 9747404Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.Type: GrantFiled: July 23, 2015Date of Patent: August 29, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Ming Kuo, Ming-Jui Chen, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen
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Publication number: 20170221897Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.Type: ApplicationFiled: April 10, 2017Publication date: August 3, 2017Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry CHE JEN HU, Ming-Jui Chen, Chen-Hsien Hsu
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Publication number: 20170178716Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.Type: ApplicationFiled: March 3, 2017Publication date: June 22, 2017Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
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Publication number: 20170162449Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
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Patent number: 9673145Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.Type: GrantFiled: September 21, 2015Date of Patent: June 6, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry Che Jen Hu, Ming-Jui Chen, Chen-Hsien Hsu
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Patent number: 9653346Abstract: An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.Type: GrantFiled: July 16, 2015Date of Patent: May 16, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry Che Jen Hu, Ming-Jui Chen, Chen-Hsien Hsu
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Patent number: 9627036Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.Type: GrantFiled: August 11, 2015Date of Patent: April 18, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
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Patent number: 9613969Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.Type: GrantFiled: July 7, 2015Date of Patent: April 4, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
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Publication number: 20170024506Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.Type: ApplicationFiled: July 23, 2015Publication date: January 26, 2017Inventors: Shih-Ming Kuo, Ming-Jui Chen, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen