Patents by Inventor Ming-Jui Chen
Ming-Jui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170024506Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.Type: ApplicationFiled: July 23, 2015Publication date: January 26, 2017Inventors: Shih-Ming Kuo, Ming-Jui Chen, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen
-
Publication number: 20170018302Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.Type: ApplicationFiled: August 11, 2015Publication date: January 19, 2017Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
-
Patent number: 9524361Abstract: A method for decomposing a layout of an integrated circuit is provided. First, a layout of the integrated circuit is imported, wherein the layout comprises a plurality of sub patterns in a cell region, and a first direction and a second direction are defined thereon. Next, one sub pattern positioned at a corner of the cell region is assigned to an anchor pattern. Then, the sub patterns in the row same as the anchor pattern along the second direction is assigned to the first group. Finally, the rest of the sub patterns are decomposed into the first group and the second group according to a design rule, wherein the sub patterns in the same line are decomposed into the first group and the second group alternatively.Type: GrantFiled: April 20, 2015Date of Patent: December 20, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ting-Cheng Tseng, Ming-Jui Chen, Chia-Wei Huang
-
Publication number: 20160351575Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.Type: ApplicationFiled: July 7, 2015Publication date: December 1, 2016Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
-
Publication number: 20160329241Abstract: An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.Type: ApplicationFiled: July 16, 2015Publication date: November 10, 2016Inventors: Shih-Chin LIN, Kuei-Chun HUNG, Jerry Che Jen HU, Ming-Jui CHEN, Chen-Hsien HSU
-
Publication number: 20160329276Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.Type: ApplicationFiled: September 21, 2015Publication date: November 10, 2016Inventors: Shih-Chin Lin, Kuei-Chun Hung, Jerry CHE JEN HU, Ming-Jui Chen, Chen-Hsien Hsu
-
Publication number: 20160306910Abstract: A method for decomposing a layout of an integrated circuit is provided. First, a layout of the integrated circuit is imported, wherein the layout comprises a plurality of sub patterns in a cell region, and a first direction and a second direction are defined thereon. Next, one sub pattern positioned at a corner of the cell region is assigned to an anchor pattern. Then, the sub patterns in the row same as the anchor pattern along the second direction is assigned to the first group. Finally, the rest of the sub patterns are decomposed into the first group and the second group according to a design rule, wherein the sub patterns in the same line are decomposed into the first group and the second group alternatively.Type: ApplicationFiled: April 20, 2015Publication date: October 20, 2016Inventors: Ting-Cheng Tseng, Ming-Jui Chen, Chia-Wei Huang
-
Patent number: 9368365Abstract: A manufacturing method for forming a semiconductor structure includes: first, a plurality of fin structures are formed on a substrate and arranged along a first direction, next, a first fin cut process is performed, so as to remove parts of the fin structures which are disposed within at least one first fin cut region, and a second fin cut process is then performed, so as to remove parts of the fin structures which are disposed within at least one second fin cut region, where the second fin cut region is disposed along at least one edge of the first fin cut region.Type: GrantFiled: May 12, 2015Date of Patent: June 14, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hsun Kuo, Ting-Cheng Tseng, Tan-Ya Yin, Chia-Wei Huang, Ming-Jui Chen
-
Publication number: 20160147140Abstract: The present invention provides a pattern verifying method. First, a target pattern is decomposed into a first pattern and a second pattern. A first OPC process is performed for the first pattern to form a first revised pattern, and a second OPC process is performed for the second pattern to form a second revised pattern. An inspection process is performed, wherein the inspection process comprises an after mask inspection (AMI) process, which comprises considering the target pattern, the first pattern and the second pattern.Type: ApplicationFiled: January 21, 2015Publication date: May 26, 2016Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee, Jian-Yuan Ma, Yan-Chun Chen
-
Patent number: 9274416Abstract: A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method.Type: GrantFiled: September 11, 2013Date of Patent: March 1, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Ming-Jui Chen, Chia-Wei Huang, Hsin-Yu Chen, Kai-Lin Chuang
-
Patent number: 9262820Abstract: A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.Type: GrantFiled: May 19, 2014Date of Patent: February 16, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee
-
Patent number: 9208276Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.Type: GrantFiled: August 11, 2015Date of Patent: December 8, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Chao Tsao, Shih-Fang Hong, Chia-Wei Huang, Ming-Jui Chen, Shih-Fang Tzou, Ming-Te Wei
-
Publication number: 20150347657Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.Type: ApplicationFiled: August 11, 2015Publication date: December 3, 2015Inventors: Po-Chao Tsao, Shih-Fang Hong, Chia-Wei Huang, Ming-Jui Chen, Shih-Fang Tzou, Ming-Te Wei
-
Publication number: 20150332449Abstract: A method for IC design is provided. Firstly, an IC design layout having a main feature with an original margin is received. Then, a first modified margin of the main feature is generated; and a first photolithography simulation procedure of the main feature with the first modified margin is performed to generate a first contour having a plurality of curves. Next, an equation of each of the curves is obtained; each equation of the curves is manipulated to obtain a vertex of each of the curves. After that, a first group of target points are assigned to the original margin. Each of the first group of target points respectively corresponds to one of the vertices. Finally, an optical proximity correction (OPC) procedure is performed by using the first group of target points to generate a second modified margin. An apparatus for IC design is also provided.Type: ApplicationFiled: May 19, 2014Publication date: November 19, 2015Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Te-Hsien HSIEH, Ming-Jui CHEN, Cheng-Te WANG, Jing-Yi LEE
-
Patent number: 9141744Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.Type: GrantFiled: August 15, 2013Date of Patent: September 22, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Chao Tsao, Shih-Fang Hong, Chia-Wei Huang, Ming-Jui Chen, Shih-Fang Tzou, Ming-Te Wei
-
Patent number: 9104833Abstract: A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth.Type: GrantFiled: May 26, 2014Date of Patent: August 11, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Fang Kuo, Ming-Jui Chen, Ting-Cheng Tseng, Cheng-Te Wang
-
Patent number: 9047658Abstract: A calculation method of optical proximity correction includes providing at least a feature pattern to a computer system. At least a first template and a second template are defined so that portions of the feature pattern are located in the first template and the rest of the feature pattern is located in the second template. The first template and the second template have a common boundary. Afterwards, a first calculation zone is defined to overlap an entire first template and portions of the feature pattern out of the first template. Edges of the feature pattern within the first calculation zone are then fragmented from the common boundary towards two ends of the feature pattern so as to generate at least two first beginning segments respectively at two sides of the common boundary. Finally, positions of the first beginning segments are adjusted so as to generate first adjusted segments.Type: GrantFiled: November 5, 2013Date of Patent: June 2, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Ping-I Hsieh, Jing-Yi Lee
-
Publication number: 20150125063Abstract: A calculation method of optical proximity correction includes providing at least a feature pattern to a computer system. At least a first template and a second template are defined so that portions of the feature pattern are located in the first template and the rest of the feature pattern is located in the second template. The first template and the second template have a common boundary. Afterwards, a first calculation zone is defined to overlap an entire first template and portions of the feature pattern out of the first template. Edges of the feature pattern within the first calculation zone are then fragmented from the common boundary towards two ends of the feature pattern so as to generate at least two first beginning segments respectively at two sides of the common boundary. Finally, positions of the first beginning segments are adjusted so as to generate first adjusted segments.Type: ApplicationFiled: November 5, 2013Publication date: May 7, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Ping-I Hsieh, Jing-Yi Lee
-
Publication number: 20150072272Abstract: A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hsien Huang, Ming-Jui Chen, Chia-Wei Huang, Hsin-Yu Chen, Kai-Lin Chuang
-
Patent number: 8966410Abstract: A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.Type: GrantFiled: October 29, 2013Date of Patent: February 24, 2015Assignee: United Microelectronics Corp.Inventors: Chia-Wei Huang, Ming-Jui Chen, Chun-Hsien Huang