Patents by Inventor Ming-Jui Chen
Ming-Jui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130280645Abstract: A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth.Type: ApplicationFiled: April 24, 2012Publication date: October 24, 2013Inventors: Hui-Fang Kuo, Ming-Jui Chen, Ting-Cheng Tseng, Cheng-Te Wang
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Publication number: 20130163850Abstract: A mask pattern and a correcting method thereof are provided. The correcting method includes the following steps. An original pattern having a first original contour and a second original contour is provided. The first original contour has a first original corner. The second original contour has a second original corner, which is near the first original corner. The first and second original corners are cut to form a cut pattern. An optical proximity correction (OPC) process is applied to the cut pattern to form the mask pattern.Type: ApplicationFiled: December 27, 2011Publication date: June 27, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Cheng-Te Wang, Jing-Yi Lee
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Patent number: 8470655Abstract: A method for designing a stressor pattern is described, wherein the stressor pattern is used to form S/D regions of a second-type MOS transistor. A first distance between a boundary of the stressor pattern and a first active area of a first-type MOS transistor is derived. If the first distance is less than a safe distance, the stressor pattern is shrunk to make the first distance at least equal to the safe distance.Type: GrantFiled: April 18, 2012Date of Patent: June 25, 2013Assignee: United Microelectronics Corp.Inventors: Chun-Hsien Huang, Ming-Jui Chen, Chia-Wei Huang, Ting-Cheng Tseng
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Patent number: 8423923Abstract: An optical proximity correction method is provided. A target pattern is provided, and then the target pattern is decomposed to a first pattern and a second pattern. The first pattern and the second pattern are alternately arranged in a dense region. Then, a compensation pattern is provided and it is determined whether the compensation pattern is added into the first pattern to become a first revised pattern, or into the second pattern to become a second revised pattern. Finally, the first revised pattern is output onto a first mask and the second revised pattern is output onto a second mask.Type: GrantFiled: July 20, 2011Date of Patent: April 16, 2013Assignee: United Microelectronics Corp.Inventors: Chia-Wei Huang, Ming-Jui Chen, Ting-Cheng Tseng, Hui-Fang Kuo
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Publication number: 20130050688Abstract: A mask inspecting method includes the following steps. A processing parameter is defined. An incident light is decided by the processing parameter. At least a portion of the incident light is emitted to and passes through a first position and a second position of a first area of a mask, to detect a first parameter and a second parameter respectively corresponding to the first position and the second position, and then the variation of the first parameter and the second parameter is compared. Additionally, at least a portion of the incident light is emitted to and passes through a third position and a fourth position of a second area of a mask, to detect a third parameter and a fourth parameter respectively corresponding to the third position and the fourth position, and then the variation of the third parameter and the fourth parameter is also compared.Type: ApplicationFiled: August 26, 2011Publication date: February 28, 2013Inventors: Wei-Cyuan Lo, Yung-Feng Cheng, Ming-Jui Chen
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Patent number: 8383299Abstract: A double patterning mask set includes a first mask having a first set of via patterns, and a second mask having a second set of via patterns. The first set of via patterns includes at least two via patterns arranged along a diagonal direction, each of the at least two via patterns has at least a truncated corner. The first set of via patterns and the second set of via patterns are interlacedly arranged along a horizontal direction and a vertical direction.Type: GrantFiled: May 17, 2011Date of Patent: February 26, 2013Assignee: United Microelectronics Corp.Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Shih-Ming Kuo, Ping-I Hsieh, Cheng-Te Wang, Jing-Yi Lee
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Publication number: 20130024824Abstract: An optical proximity correction method is provided. A target pattern is provided, and then the target pattern is decomposed to a first pattern and a second pattern. The first pattern and the second pattern are alternately arranged in a dense region. Then, a compensation pattern is provided and it is determined whether the compensation pattern is added into the first pattern to become a first revised pattern, or into the second pattern to become a second revised pattern. Finally, the first revised pattern is output onto a first mask and the second revised pattern is output onto a second mask.Type: ApplicationFiled: July 20, 2011Publication date: January 24, 2013Inventors: Chia-Wei Huang, Ming-Jui Chen, Ting-Cheng Tseng, Hui-Fang Kuo
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Publication number: 20120319287Abstract: A method for fabricating a semiconductor layout includes providing a first layout having a plurality of line patterns and a second layout having a plurality of connection patterns, defining at least a first to-be-split pattern overlapping with the connection pattern among the line patterns, splitting the first to-be-split pattern at where the first to-be-split pattern overlapping with the connection pattern, decomposing the first layout to form a third layout and a fourth layout, and outputting the third layout and the further layout to a first mask and a second mask respectively.Type: ApplicationFiled: June 20, 2011Publication date: December 20, 2012Inventors: Chia-Wei Huang, Ming-Jui Chen, Chun-Hsien Huang
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Patent number: 8321820Abstract: A method to compensate optical proximity correction adapted for a photolithography process includes providing an integrated circuit (IC) layout. The IC layout includes active regions, a shallow trench isolation (STI) region and ion implant regions overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region disposed in the STI region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side. Then, the corrected IC layout is transferred to a photomask.Type: GrantFiled: February 22, 2012Date of Patent: November 27, 2012Assignee: United Microelectronics Corp.Inventors: Chun-Hsien Huang, Ming-Jui Chen, Te-Hung Wu, Yu-Shiang Yang
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Patent number: 8321822Abstract: A method optical proximity correction includes the following steps. First, a layout of an integrated circuit with an exposure intensity specification is provided. The integrated circuit includes a plurality of patterns and each pattern has an exposure intensity distribution. Second, a quadratic polynomial equation of each exposure intensity distribution is approximated. Third, a local extreme intensity of each exposure intensity distribution is computed by fitting the quadratic polynomial equation. Fourth, the local extreme intensity is determined whether violating the exposure intensity specification or not. Then, the layout is corrected when the local extreme intensity violates the exposure intensity specification.Type: GrantFiled: May 27, 2010Date of Patent: November 27, 2012Assignee: United Microelectronics Corp.Inventors: Yu-Shiang Yang, Ming-Jui Chen, Te-Hung Wu
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Publication number: 20120295186Abstract: A double patterning mask set includes a first mask having a first set of via patterns, and a second mask having a second set of via patterns. The first set of via patterns includes at least two via patterns arranged along a diagonal direction, each of the at least two via patterns has at least a truncated corner. The first set of via patterns and the second set of via patterns are interlacedly arranged along a horizontal direction and a vertical direction.Type: ApplicationFiled: May 17, 2011Publication date: November 22, 2012Inventors: Te-Hsien Hsieh, Ming-Jui Chen, Shih-Ming Kuo, Ping-I Hsieh, Cheng-Te Wang, Jing-Yi Lee
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Publication number: 20120192123Abstract: A method to compensate optical proximity correction adapted for a photolithography process includes providing an integrated circuit (IC) layout. The IC layout includes active regions, a shallow trench isolation (STI) region and ion implant regions overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region disposed in the STI region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side. Then, the corrected IC layout is transferred to a photomask.Type: ApplicationFiled: February 22, 2012Publication date: July 26, 2012Inventors: Chun-Hsien Huang, Ming-Jui Chen, Te-Hung Wu, Yu-Shiang Yang
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Patent number: 8151221Abstract: A method to compensate optical proximity correction adapted for a photolithography process is provided. An integrated circuit (IC) layout firstly is provided. The IC layout includes active regions and a shallow trench isolation (STI) region. The STI region is a region except the active regions. The IC layout further includes ion implant regions which are overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Each photoresist line width compensation region is disposed in the STI region. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side.Type: GrantFiled: April 29, 2010Date of Patent: April 3, 2012Assignee: United Microelectronics Corp.Inventors: Chun-Hsien Huang, Ming-Jui Chen, Te-Hung Wu, Yu-Shiang Yang
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Publication number: 20110296359Abstract: A method optical proximity correction includes the following steps. First, a layout of an integrated circuit with an exposure intensity specification is provided. The integrated circuit includes a plurality of patterns and each pattern has an exposure intensity distribution. Second, a quadratic polynomial equation of each exposure intensity distribution is approximated. Third, a local extreme intensity of each exposure intensity distribution is computed by fitting the quadratic polynomial equation. Fourth, the local extreme intensity is determined whether violating the exposure intensity specification or not. Then, the layout is corrected when the local extreme intensity violates the exposure intensity specification.Type: ApplicationFiled: May 27, 2010Publication date: December 1, 2011Inventors: Yu-Shiang YANG, Ming-Jui Chen, Te-Hung Wu
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Publication number: 20110271237Abstract: A method to compensate optical proximity correction adapted for a photolithography process is provided. An integrated circuit (IC) layout firstly is provided. The IC layout includes active regions and a shallow trench isolation (STI) region. The STI region is a region except the active regions. The IC layout further includes ion implant regions which are overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Each photoresist line width compensation region is disposed in the STI region. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side.Type: ApplicationFiled: April 29, 2010Publication date: November 3, 2011Inventors: Chun-Hsien HUANG, Ming-Jui CHEN, Te-Hung WU, Yu-Shiang YANG
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Publication number: 20080070408Abstract: The invention is directed to a method for adjusting sizes and shapes of plug openings for border plug openings overlapping with trenches respectively, wherein the border plug openings are separated from each other with a distance equal to or smaller than a specific distance. The method comprises performing an adjusting process for separating the border plug openings away from each other and enlarging the dimensions of the border plug openings so that the border plug openings are located within the trenches respectively and the edges of the borer openings are separated from the sidewalks of the trenches, wherein the border plug openings are enlarged within ranges of the trenches respectively.Type: ApplicationFiled: May 24, 2006Publication date: March 20, 2008Inventors: Chin-Lung Lin, Ming-Jui Chen, Chen-yu Ao, Hung-Chin Thuang, Jen-Hsiang Tsai, Jian-Shin Liou
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Patent number: 7312020Abstract: A lithography method for forming a plurality of patterns in a photoresist layer. A phase shift mask including a plurality of transparent main features, a plurality of first phase shift transparent regions, and a plurality of second phase shift transparent regions is provided. Each transparent main feature is surrounded by the first phase shift transparent regions and the second phase shift transparent regions interlaced contiguously along a periphery of the transparent main feature. Each of the first phase shift transparent regions has a phase shift relative to each of the second phase shift transparent regions. An exposure process is performed to irradiate the phase shift mask with light so that the patterns corresponding to the transparent main features are formed in the photoresist layer.Type: GrantFiled: November 10, 2003Date of Patent: December 25, 2007Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Chuen Huei Yang, Ming-Jui Chen, Venson Lee
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Patent number: 7141337Abstract: A phase shift mask includes a transparent substrate, a semi-dense pattern, and a dense pattern. The semi-dense pattern is formed on the transparent substrate including a plurality of phase shift regions and non-phase shift regions arranged successively. The dense pattern is formed on the transparent substrate including a plurality of non-phase shift regions, phase shift regions, and non-transparent regions.Type: GrantFiled: April 3, 2003Date of Patent: November 28, 2006Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Chuen-Huei Yang, Ming-Jui Chen, Wen-Tien Hung
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Patent number: 7116815Abstract: A chrome-less mask inspection method is provided. The chrome-less mask at least includes a transparent region and a phase shift region. The method includes providing a database having a mask database corresponding to the chrome-less mask. The mask database further includes a frame line pattern having enclosed area and pattern that corresponds to enclosed area and pattern of the phase shift region of the chrome-less mask and a first inspection signal pattern generated by the mask database. An inspecting device is also provided to inspect a second inspection signal pattern from the chrome-less mask. Furthermore, scanning location of the second inspection signal pattern corresponds with scanning location of the first inspection signal pattern. Thereafter, the first inspection signal pattern and the second inspection signal pattern is compared and any differences are registered.Type: GrantFiled: May 9, 2003Date of Patent: October 3, 2006Assignee: United Microelectronics Corp.Inventors: Ming-Jui Chen, Chin-Lung Lin
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Publication number: 20050100829Abstract: A lithography method for forming a plurality of patterns in a photoresist layer. A phase shift mask including a plurality of transparent main features, a plurality of first phase shift transparent regions, and a plurality of second phase shift transparent regions is provided. Each transparent main feature is surrounded by the first phase shift transparent regions and the second phase shift transparent regions interlaced contiguously along a periphery of the transparent main feature. Each of the first phase shift transparent regions has a phase shift relative to each of the second phase shift transparent regions. An exposure process is performed to irradiate the phase shift mask with light so that the patterns corresponding to the transparent main features are formed in the photoresist layer.Type: ApplicationFiled: November 10, 2003Publication date: May 12, 2005Inventors: Chin-Lung Lin, Chuen Huei Yang, Ming-Jui Chen, Venson Lee