Patents by Inventor Ming Lee

Ming Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230326772
    Abstract: A method includes moving a drum containing a chemical liquid into a chamber of a chemical liquid supplying system. The drum is connected with a testing pipe. The chemical liquid is pumped from the drum to the testing pipe. A condition of the chemical liquid flowing through the testing pipe is monitored. Whether the chemical liquid is supplied to a processing tool is determined based on the condition of the chemical liquid.
    Type: Application
    Filed: June 9, 2023
    Publication date: October 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Cheng CHANG, Keng-Hui PAN, Chieh-Jan HUANG, Ming-Lee LEE, Chiang-Jeh CHEN
  • Publication number: 20230327021
    Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 12, 2023
    Inventors: Chao-Hsun Wang, Chen-Ming Lee, Kuo-Yi Chao, Mei-Yun Wang, Pei-Yu Chou, Kuo-Ju Chen
  • Patent number: 11784222
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Publication number: 20230317457
    Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Inventors: Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu, Hsin-Yun Hsu, Pin-Hsuan Yeh
  • Publication number: 20230317805
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.
    Type: Application
    Filed: March 21, 2022
    Publication date: October 5, 2023
    Inventors: Shih-Che LIN, Tzu-Yang HO, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Patent number: 11771651
    Abstract: Disclosed herein are novel synthetic polypeptides and uses thereof in the preparation of liposomes. According to embodiments of the present disclosure, the synthetic polypeptide comprises a membrane lytic motif, a masking motif, and a linker configured to link the membrane lytic motif and the masking motif. The linker is cleavable by a stimulus, such as, light, protease, or phosphatase. Once being coupled to a liposome, the exposure to the stimulus cleaves the linker that results in the separation of the masking motif from the membrane lytic motif, which in turn exerts membrane lytic activity on the liposome that leads to the collapse of the intact structure of the liposome, and releases the agent encapsulated in the liposome to the target site. Also disclosed herein are methods of diagnosing or treating a disease in a subject by use of the present liposomes.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: October 3, 2023
    Assignee: Academia Sinica
    Inventors: Hsien-Ming Lee, Hua-De Gao, Jia-Lin Hong, Chih-Yu Kuo, Cheng-Bang Jian
  • Patent number: 11777004
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, I-Wen Wu, Chen-Ming Lee, Jian-Hao Chen, Fu-Kai Yang, Feng-Cheng Yang, Mei-Yun Wang, Yen-Ming Chen
  • Patent number: 11772030
    Abstract: A miniature gas detection and purification device is disclosed for a user to carry with himself, and includes a main body, a purification module, a gas guider and a gas detection module. The gas detection module detects gas of surrounding environment to obtain a gas detection datum, and controls the gas guider to be operated according to the gas detection datum, so that gas is inhaled into the main body and flows through the purification module for filtration and purification, and the gas purified is finally guided to a region close to the user.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: October 3, 2023
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Yang Ku
  • Patent number: 11770913
    Abstract: A heat-dissipating component for a mobile device includes a case body, a micro pump, and a heat dissipation tube plate. The case body has a vent hole and a positioning accommodation trough. The bottom of the positioning accommodation trough is in communication with the vent hole. The micro pump is disposed in the positioning accommodation trough and corresponds to the vent hole The heat dissipation tube plate has cooling fluid inside. One end of the heat dissipation tube plate is fixed on the positioning accommodation trough and contacts a heating element of the mobile device. The gas transmitted by the micro pump forms gas flow so as to perform heat exchange with heat absorbed by the heat dissipation tube plate, and the gas flow is discharged out through the vent hole.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: September 26, 2023
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ching-Sung Lin, Chin-Chuan Wu, Chih-Kai Chen, Yung-Lung Han, Chi-Feng Huang, Wei-Ming Lee
  • Patent number: 11753060
    Abstract: A purification device of baby carriage is provided and includes a main body, a purification unit, a gas guider and a gas detection module. The purification unit, the gas guider and the gas detection module are disposed in the main body to guide the gas outside the main body through the purification unit for filtering and purifying the gas, and discharge a purified gas. The gas detection module detects particle concentration of suspended particles contained in the purified gas. The gas guider is controlled to operate and export a gas at an airflow rate within 3 minutes. The particle concentration of the suspended particles contained in the purified gas, which is filtered by the purification unit, is reduced to and less than 0.75 ?g/m3. Consequently, the purified gas is filtered, and the baby inside the baby carriage can breathe with safety.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: September 12, 2023
    Assignee: Microjet Technology Co., Ltd.
    Inventors: Hao-Jan Mou, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
  • Patent number: 11757022
    Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Heng Wang, Chun-Han Chen, I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11756913
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chi Chen, Hsun-Ying Huang, Chih-Ming Lee, Shang-Yen Wu, Chih-An Yang, Hung-Wei Ho, Chao-Ching Chang, Tsung-Wei Huang
  • Publication number: 20230282482
    Abstract: A method of manufacturing a semiconductor device includes forming a gate trench over a semiconductor substrate, depositing a gate dielectric layer and a work function layer in the gate trench, depositing a capping layer over the work function layer, passivating a surface portion of the capping layer to form a passivation layer, removing the passivation layer, depositing a fill layer in the gate trench, recessing the fill layer and the capping layer, and forming a contact metal layer above the capping layer in the gate trench.
    Type: Application
    Filed: June 4, 2022
    Publication date: September 7, 2023
    Inventors: Tsung-Han Shen, Kevin Chang, Yu-Ming Li, Chih-Hsiang Fan, Yi-Ting Wang, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
  • Patent number: 11749719
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ruei-Ping Lin, Kai-Di Tzeng, Chen-Ming Lee, Wei-Yang Lee
  • Patent number: 11746772
    Abstract: A miniature fluid transportation device is provided and includes a convergence component, a valve component, an outlet plate and a plurality of fluid transportation actuation components. The plurality of fluid transportation actuation components are disposed on the convergence component so as to transport the fluid to the convergence component. The convergence component guides the fluid transported by the fluid transportation actuation components to the outlet plate through the valve component. The outlet plate guides the fluid from different transportation actuation components back to the convergence component by a separation guiding block. The fluid is converged in a convergence central slot of the convergence component and is discharged out through a collection channel of the outlet plate. Consequently, the problem of interference owing to the convergence of the fluid transported by different fluid transportation actuation components can be avoided.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: September 5, 2023
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Chung-Wei Kao, Shih-Chang Chen, Chi-Chang Yang, Jyun-Yi Jhang, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
  • Patent number: 11744474
    Abstract: A blood pressure measurement module is provided and includes a base, a valve plate, a top cover, a micro pump, a driving circuit board and a pressure sensor. The valve plate is disposed between the base and the top cover. The micro pump is disposed within the base. The pressure sensor is disposed on the driving circuit board. An air inlet groove and the pressure sensor are connected to an airbag. The micro pump is actuated to make the airbag be inflated and oppress the skin of a user. The pressure sensor detects the pressure change within the airbag to measure the blood pressure of the user.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: September 5, 2023
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ching-Sung Lin, Wen-Yang Yang, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee
  • Publication number: 20230274983
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Patent number: 11742400
    Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an isolation structure formed over a substrate, and a gate structure formed over the isolation structure. The FinFET device structure includes a first dielectric layer formed over the isolation structure and adjacent to the gate structure and a source/drain (S/D) contact structure formed in the first dielectric layer. The FinFET device structure also includes a deep contact structure formed through the first dielectric layer and adjacent to the S/D contact structure. The deep contact structure is through the isolation structure, and a bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting Fang, Da-Wen Lin, Fu-Kai Yang, Chen-Ming Lee, Mei-Yun Wang
  • Publication number: 20230268411
    Abstract: A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan LEE, Shih-Che LIN, Po-Yu HUANG, Shih-Chieh WU, I-Wen WU, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20230268417
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 24, 2023
    Inventors: Shu-Ming LEE, Yung-Han CHIU, Chia-Hung LIU, Tzu-Ming OU YANG