Patents by Inventor Ming Liang

Ming Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210288047
    Abstract: Various embodiments of the present application are directed towards a semiconductor device comprising a trench capacitor, the trench capacitor comprising a plurality of lateral protrusions. In some embodiments, the trench capacitor comprises a dielectric structure over a substrate. The dielectric structure may comprise a plurality of dielectric layers overlying the substrate. The dielectric structure may comprise a plurality of lateral recesses. In some embodiments, the plurality of lateral protrusions extend toward and fill the plurality of lateral recesses. By forming the trench capacitor with the plurality of lateral protrusions filling the plurality of lateral recesses, the surface area of the capacitor is increased without increasing the depth of the trench. As a result, greater capacitance values may be achieved without necessarily increasing the depth of the trench and thus, without necessarily increasing the size of the semiconductor device.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 16, 2021
    Inventors: Ru-Liang Lee, Ming Chyi Liu, Shih-Chang Liu
  • Patent number: 11121563
    Abstract: A power control circuit is disclosed. The power control circuit includes a first receiving circuit, a second receiving circuit, a first power supply circuit and a second power supply circuit. The first receiving circuit is electrically connected to a charging circuit and a first port and configured to charge a power unit according to a first port voltage. The second receiving circuit is electrically connected to the charging circuit and a second port and configured to charge the power unit according to a second port voltage. The second receiving circuit is further configured to be disabled according to the first port voltage. The first power supply circuit is configured to supply power to the first port. The second power supply circuit is configured to supply power to the second port. Thus, the power control circuit transmits power or data through different ports.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 14, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Kian-Ming Chee, Kai-Chun Liang, Tao Chen, Wei-Chen Tu
  • Publication number: 20210278523
    Abstract: Systems and methods for integrating radar and LIDAR data are disclosed. In particular, a computing system can access radar sensor data and LIDAR data for the area around the autonomous vehicle. The computing system can determine, using the one or more machine-learned models, one or more objects in the area of the autonomous vehicle. The computing system can, for a respective object, select a plurality of radar points from the radar sensor data. The computing system can generate a similarity score for each selected radar point. The computing system can generate weight associated with each radar point based on the similarity score. The computing system can calculate predicted velocity for the respective object based on a weighted average of a plurality of velocities associated with the plurality of radar points. The computing system can generate a proposed motion plan based on the predicted velocity for the respective object.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 9, 2021
    Inventors: Raquel Urtasun, Bin Yang, Ming Liang, Sergio Casas, Runsheng Benson Guo
  • Publication number: 20210278852
    Abstract: Systems and methods for generating attention masks are provided. In particular, a computing system can access sensor data and map data for an area around an autonomous vehicle. The computing system can generate a voxel grid representation of the sensor data and map data. The computing system can generate an attention mask based on the voxel grid representation. The computing system can generate, by using the voxel grid representation and the attention mask as input to a machine-learned model, an attention weighted feature map. The computing system can determine using the attention weighted feature map, a planning cost volume for an area around the autonomous vehicle. The computing system can select a trajectory for the autonomous vehicle based, at least in part, on the planning cost volume.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 9, 2021
    Inventors: Raquel Urtasun, Bob Qingyuan Wei, Mengye Ren, Wenyuan Zeng, Ming Liang, Bin Yang
  • Publication number: 20210276587
    Abstract: Systems and methods of the present disclosure are directed to a method. The method can include obtaining simplified scenario data associated with a simulated scenario. The method can include determining, using a machine-learned perception-prediction simulation model, a simulated perception-prediction output based at least in part on the simplified scenario data. The method can include evaluating a loss function comprising a perception loss term and a prediction loss term. The method can include adjusting one or more parameters of the machine-learned perception-prediction simulation model based at least in part on the loss function.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 9, 2021
    Inventors: Raquel Urtasun, Kelvin Ka Wing Wong, Qiang Zhang, Bin Yang, Ming Liang, Renjie Liao
  • Patent number: 11114436
    Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chi Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11109645
    Abstract: Systems and methods for monitoring the quality of a surface treatment applied to an article in a manufacturing process are provided. A surface treatment may be applied to at least a portion of an article. A thermal profile of the article may be obtained and used to determine temperature indications of different regions of the article to which the surface treatment has been applied. A standard model of the article may be obtained that includes model regions having model temperature ranges. The temperature indications of the article can be compared with the model temperature ranges to determine if any temperature indications are outside of a corresponding model temperature range. The article may be a shoe part. The surface treatments may include the application of heat, plasma, dye, paint, primer, and/or the application of other materials, substances, and/or processes.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 7, 2021
    Assignee: NIKE, Inc.
    Inventors: Dragan Jurkovic, Chun-Wei Huang, Jen-Chuan Lin, Shih-Yuan Wu, Chih-Chun Chai, Ming-Ji Lee, Chien-Liang Yeh
  • Patent number: 11114347
    Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a semiconductor device includes a first gate structure and a second gate structure on a substrate; wherein the first gate structure includes a first gate dielectric layer having a first material, and the second gate structure includes a second gate dielectric layer having a second material, the first material being different from the second material, wherein the first and the second gate structures further comprises a first and a second self-protective layers disposed on the first and the second gate dielectric layers respectively, wherein the first self-protective layer comprises metal phosphate and the second self-protective layer comprises boron comprising complex agents and a first work function tuning layer on the first self-protective layer in the first gate structure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20210273600
    Abstract: A photovoltaic module includes an encapsulated photovoltaic element and an infrared-transmissive decorative overlay simulating conventional roofing.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Husnu M. Kalkanoglu, Gregory F. Jacobs, Ming Liang Shiao
  • Publication number: 20210273069
    Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.
    Type: Application
    Filed: July 15, 2020
    Publication date: September 2, 2021
    Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
  • Publication number: 20210273138
    Abstract: The present application discloses a light-emitting device comprises a semiconductor light-emitting element, a transparent element covering the semiconductor light-emitting element, an insulating layer which connects to the transparent element, an intermediate layer which connects to the insulating layer; and a conductive adhesive material connecting to the intermediate layer.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Chien-Liang LIU, Ming-Chi HSU, Shih-An LIAO, Jen-Chieh YU, Min-Hsun HSIEH, Jia-Tay KUO, Yu-His SUNG, Po-Chang CHEN
  • Publication number: 20210267318
    Abstract: Systems and methods for monitoring the quality of a surface treatment applied to an article in a manufacturing process are provided. A surface treatment may be applied to at least a portion of an article. A thermal profile of the article may be obtained and used to determine temperature indications of different regions of the article to which the surface treatment has been applied. A standard model of the article may be obtained that includes model regions having model temperature ranges. The temperature indications of the article can be compared with the model temperature ranges to determine if any temperature indications are outside of a corresponding model temperature range. The article may be a shoe part. The surface treatments may include the application of heat, plasma, dye, paint, primer, and/or the application of other materials, substances, and/or processes.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Inventors: Dragan Jurkovic, Chun-Wei Huang, Jen-Chuan Lin, Shih-Yuan Wu, Chih-Chun Chai, Ming-Ji Lee, Chien-Liang Yeh
  • Publication number: 20210273095
    Abstract: A low specific on-resistance (Ron,sp) power semiconductor device includes a power device and a transient voltage suppressor (TVS); wherein the power device comprises a gate electrode, a drain electrode, a bulk electrode, a source electrode and a parasitic body diode, the bulk electrode and the source electrode are shorted, the TVS comprises an anode electrode and a cathode electrode, the drain electrode of the power device and the anode electrode of the TVS are connected by a first metal to form a high-voltage terminal electrode, the source electrode of the power device and the cathode electrode of the TVS are connected by a second metal to form a low-voltage terminal electrode.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 2, 2021
    Applicant: University of Electronic Science and Technology of China
    Inventors: Ming QIAO, Longfei LIANG, Yilei LYU, Zhao QI, Bo Zhang
  • Patent number: 11107921
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
  • Patent number: 11106396
    Abstract: A memory apparatus and compensation method for a computation result thereof are provided. The memory apparatus includes a memory sub-block, a reference memory sub-block and a control circuit. During a computation phase, the memory sub-block receives an input signal, and generates a computation result by a multiply-accumulate operation according to the input signal. The reference memory sub-block includes a plurality of memory cells pre-programmed with a reference weight value. The reference memory sub-block receives a reference input signal during a calibration phase, and generates a reference computation value by a multiply-accumulate operation according to the reference input signal and the reference weight value. The control circuit generates an adjustment value according to the reference computation value and a standard computation value, and during the computation phase, adjusts the computation result according to the adjustment value to generate an adjusted computation result.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: August 31, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Kai Hsu, Teng-Hao Yeh, Ming-Liang Wei, Hang-Ting Lue
  • Patent number: 11107902
    Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Gang Chen, Tai-Chun Huang, Yi-Ting Fu, Ming-Chang Wen, Shu-Yuan Ku, Fu-Kai Yang, Tze-Liang Lee, Yung-Cheng Lu
  • Publication number: 20210262232
    Abstract: This invention, in embodiments, relates to a roofing material having (a) a front surface, (b) a back surface, and (c) a sealant attachment zone disposed on at least the front surface of the roofing material, the sealant attachment zone including surfacing media that comprise at least one of mineral particles, polymeric particles, and combinations thereof. The sealant attachment zone has an average surface coverage of the surfacing media of 30% to 70%. The roofing material exhibits an increased wind uplift resistance, as measured according to ASTM D6381, as compared to a roofing material without a sealant attachment zone having an average surface coverage of surfacing media of 30% to 70%.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 26, 2021
    Inventors: Ming-Liang Shiao, Joey Ferraro, Luis Duque, Brian Lee, Tim Lock, Daniel E. Boss
  • Publication number: 20210265142
    Abstract: A method for processing semiconductor wafer is provided. The method includes loading a semiconductor wafer on a top surface of a wafer chuck. The method also includes supplying a gaseous material between the semiconductor wafer and the top surface of the wafer chuck through a first gas inlet port and a second gas inlet port located underneath a fan-shaped sector of the top surface. The method further includes supplying a fluid medium to a fluid inlet port of the wafer chuck and guiding the fluid medium from the fluid inlet port to flow through a number of arc-shaped channels located underneath the fan-shaped sector of the top surface. In addition, the method includes supplying a plasma gas over the semiconductor wafer.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 26, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Chun YANG, Yi-Ming LIN, Po-Wei LIANG, Chu-Han HSIEH, Chih-Lung CHENG, Po-Chih HUANG
  • Publication number: 20210262609
    Abstract: A gimbal includes a control device configured to receive an action instruction including a press action instruction and, based on the action instruction, generate a control instruction including a switch control instruction for switching operating modes of the gimbal, a controlling assembly configured to receive the control instruction and generate a performing instruction based on the control instruction for controlling an optical device, and a performing assembly configured to receive and implement the performing instruction. The performing assembly is operably connected to the controlling assembly and supported on a top end of a support arm of the control device. The performing assembly comprises a first rotation member, a second rotation member, and a carrying member connected one to another, and first and second motors for driving the second rotation member and the carrying member to rotate relative to the first and second rotation members, respectively.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Inventors: Paul PAN, Ming Liang ZHU, Xi Feng ZHAO
  • Patent number: 11101441
    Abstract: A quantum dot light-emitting diode includes a substrate, an anode electrode layer, a cathode electrode layer, a light-emitting layer, and an electron blocking layer. The anode electrode layer is disposed on the substrate. The cathode electrode layer is disposed on the anode electrode layer. The light-emitting layer is disposed between the cathode electrode layer and the anode electrode layer. The light-emitting layer includes a plurality of first particles. The electron blocking layer is disposed between the light-emitting layer and the anode electrode layer. The electron blocking layer includes a plurality of second particles. The first particles and the second particles are quantum dots. A size of the second particles is smaller than a size of the first particles.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 24, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Ming-Cheng Kuo, Yao-Shan Chang, Po-Liang Chen, Chin-Cheng Tsai, Yi-Ju Hsiao, Ya-Pei Kuo