Patents by Inventor Ming Liu

Ming Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240384571
    Abstract: A smart lock for securing a bicycle to a bicycle rack is provided. The smart lock comprises a bicycle rack attachment, configured to attach the smart lock to the bicycle rack. The smart lock further comprises a smart locking mechanism, distinct from the bicycle rack attachment, configured to permit an authorised user to releasably secure the bicycle to the smart lock.
    Type: Application
    Filed: July 13, 2022
    Publication date: November 21, 2024
    Inventors: Simon Laumet, Chiu-Ming Liu
  • Publication number: 20240387247
    Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun LIU, Chin-Hsiang LIN, Chih-Ming LAI, Wei-Liang LIN, Yung-Sung YEN
  • Publication number: 20240387348
    Abstract: A display panel includes a first substrate, first electrodes, connection leads, a connection layer, a second substrate, and second electrodes disposed on a side of the second substrate away from the first substrate. The first substrate includes a first surface and a second surface that are opposite to each other and side surfaces connecting the first and second surfaces. At least one side surface is a selected side surface. The second substrate is disposed on the second surface. The connection layer bonds the first substrate and the second substrate. An orthographic projection of the connection layer on the second surface is located within an orthographic projection of the second substrate on the second surface. The connection leads extend from the first surface to the second surface through the selected side surface. Two ends of a connection lead are connected to a first electrode and a second electrode, respectively.
    Type: Application
    Filed: May 16, 2024
    Publication date: November 21, 2024
    Applicants: BOE MLED Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Chao LIU, Mengqing LIU, Zhonglan ZHAO, Lili WANG, Jingping ZHAO, Shanshan FENG, Mingming JIA, Jing WANG, Sha FENG, Huaimin WANG, Qi QI, Ming ZHAI, Haiwei SUN
  • Patent number: 12148653
    Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Chin-Hsiang Lin, Chih-Ming Lai, Wei-Liang Lin, Yung-Sung Yen
  • Publication number: 20240375318
    Abstract: Provided is a multi-tow carbon fiber spreading and pre-impregnation system, which is used to solve the technical problems of large thickness, high porosity and the like of a prepreg tape product caused by low spread ratio and insufficient pre-impregnation in the production process of existing thermoplastic prepreg tapes. The system includes a filament release module, a filament doubling module, an airflow spreading module, a process deviation correction module, a traction module, a slurry impregnation module, an infrared melting module, a hot-pressing shaping module, a floating roller module, a cutting module, a leftover collecting module, a winding deviation correction module and a winding module which are sequentially arranged along a feeding direction. The filament release module includes at least two filament release assemblies, and carbon fibers are placed on the filament release assemblies.
    Type: Application
    Filed: September 8, 2022
    Publication date: November 14, 2024
    Inventors: MING HUANG, YANG WANG, CHUNTAI LIU, NA ZHANG, JUN ZHOU, YUNQIU ZU, XIANZHANG SHI, WEI WEI
  • Publication number: 20240379463
    Abstract: In a method of inspection of a semiconductor substrate a first beam of light is split into two or more second beams of light. The two or more second beams of light are respectively transmitted onto a first set of two or more first locations on top of the semiconductor substrate. In response to the transmitted two or more second beams of light, two or more reflected beams of light from the first set of two or more first locations are received. The received two or more reflected beams of light are detected to generate two or more detected signals. The two or more detected signals are analyzed to determine whether a defect exists at the set of the two or more first locations.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng He HUANG, Chung-Pin CHOU, Shiue-Ming GUO, Hsuan-Chia KAO, Yan-Cheng CHEN, Sheng-Ching KAO, Jun Xiu LIU
  • Publication number: 20240381637
    Abstract: A field effect transistor includes a source region and a drain region embedded in a portion of a semiconductor substrate; a gate dielectric overlying a channel region located between the source region and the drain region; a gate electrode overlying the gate dielectric; a dielectric gate liner laterally surrounding the gate electrode; a inner gate spacer laterally surrounding the dielectric gate liner; a contoured gate capping dielectric including a vertically-extending portion that laterally surrounds the inner gate spacer and a horizontally-extending portion that overlies the gate electrode; and a outer gate spacer laterally surrounding the contoured gate capping dielectric.
    Type: Application
    Filed: May 9, 2023
    Publication date: November 14, 2024
    Inventors: Yu-Hsiang Yang, Chen-Ming Huang, Po-Wei Liu, Shih-Hsien Chen, Hung-Ling Shih, Chang Hung-Chang
  • Publication number: 20240377732
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes a chemical formula of MaXbLc, where M is a metal, X is a multidentate aromatic ligand that includes a pyrrole-like nitrogen and a pyridine-like nitrogen, L is an extreme ultraviolet (EUV) cleavable ligand, a is between 1 and 2, b is equal to or greater than 1, and c is equal to or greater than 1.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Publication number: 20240379854
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew -Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Chiang, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Publication number: 20240379358
    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 12143109
    Abstract: A device for correcting a duty cycle, comprising: a duty adjustor circuit, configured to receive an input clock signal and a tuning signal, to generate an output clock signal; a first charge pump, configured to charge a first capacitor for a predetermined time period to generate a first voltage; a second charge pump, configured to charge a second capacitor for a time period corresponding to the duty cycle of the output clock signal to generate a second voltage; a first sampling and hold circuit, configured to sample the first voltage to generate a first sampled voltage; a second sampling and hold circuit, configured to sample the second voltage to generate a second sampled voltage; and an error amplifier, configured to generate the tuning signal according to a difference value between the first sampled voltage and the second sampled voltage.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: November 12, 2024
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Ming Wang, Kun Lan, Cong Liu
  • Patent number: 12143333
    Abstract: A method for sending a wireless local area network packet structure is provided, and the method comprises: determining a packet structure, where the packet structure comprises an HE-SIGA and an HE-SIGB, the HE-SIGA comprises an indication information, and if a current transmission mode is a full bandwidth MU-MIMO transmission, the indication information is used to indicate a number of scheduled users, or if the current transmission mode is other transmission mode, the indication information is used to indicate a number of symbols in the HE-SIGB; and sending the packet structure.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: November 12, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Meilu Lin, Ming Gan, Le Liu, Jun Zhu, Jian Yu
  • Patent number: 12141359
    Abstract: A vibration feedback device and control method thereof are provided. The vibration feedback device includes a substrate, a frame and a plurality of displacement restoration devices; one end of each displacement restoration device is connected to the frame, and the other end is connected to the substrate; one side of the substrate is the user operation surface, and the other side includes at least one driving coil, at least one induction coil, a controller and a driver; the frame also includes a first magnet set corresponding to the driving coil and a second magnet set corresponding to the induction coil; the controller processes the signal obtained by the induction coil to drive the vibration feedback device to achieve a reliable vibration suppression effect.
    Type: Grant
    Filed: September 12, 2023
    Date of Patent: November 12, 2024
    Assignee: TOPRAY MEMS INC.
    Inventors: Chin-Sung Liu, Tzu-Kuang Fang, Hsiao-Ming Chien, Shin-Ter Tsai
  • Patent number: 12142514
    Abstract: A clamp ring including an inner periphery of increased diameter at locations where inwardly extending tabs are not located reduces the risk a workpiece that is placed in close proximity to the clamp ring or which contacts the clamp ring during processing will stick to the clamp ring.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Chou, Yuan-Hsin Chi, Yin-Tun Chou, Hung-Chih Wang, Yu-Chi Liu, Chih-Ming Wang
  • Patent number: 12141505
    Abstract: An optimization method of shield tunnel starting end reinforcement solution, which specifically includes the following steps: acquiring shield tunnel engineering data and temperature variation curves of thermometer holes; constructing a numerical model with thermal convection and a hydro-thermal coupling numerical model respectively according to the shield tunnel engineering data, wherein a first temperature variation curve and a second temperature variation curve can be obtained after carrying out numerical simulations on the above two models; the influence of seepage on the development law of a temperature field can be obtained by comparing and analyzing the temperature variation curves of the thermometer holes with the first and the second temperature variation curves; and finally the existing freezing solution of the shield tunnel is optimized according to the influence of the seepage on the development law of the temperature field, to ensure safe use of the shield tunnel.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: November 12, 2024
    Assignee: HAINAN UNIVERSITY
    Inventors: Jun Hu, Jianjian Zhan, Wenbo Liu, Lu Chen, Ming Xiong, Hongshuo Zhang, Zhixin Wang, Hui Zeng, Lin Jia
  • Patent number: 12139580
    Abstract: The present invention discloses a class of nitrogen-containing heterocyclic polymers, a class of polymer membranes and applications thereof, wherein the nitrogen-containing heterocyclic polymers comprise structural units of following general formula: A nitrogen-containing heterocycles in the class of nitrogen-containing heterocyclic polymers have large steric hindrance and electron donating groups, which are beneficial for further improving stability of materials. The class of nitrogen-containing heterocyclic polymers can be formed membranes using commonly industrial methods such as coating.
    Type: Grant
    Filed: June 19, 2024
    Date of Patent: November 12, 2024
    Assignee: WUHAN LIMO TECHNOLOGY CO., LTD
    Inventors: Ming Li, Junyu Liu, Yunlan Liao
  • Publication number: 20240369759
    Abstract: Disclosed are semiconductor packages and manufacturing method of the semiconductor packages. In one embodiment, a semiconductor package includes a substrate, a first waveguide, a semiconductor die, and an adhesive layer. The first waveguide is disposed on the substrate. The semiconductor die is disposed on the substrate and includes a second waveguide aligned with the first waveguide. The adhesive layer is disposed between the first waveguide and the second waveguide.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Hua-Kuei Lin, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Che-Hsiang Hsu, Chewn-Pu Jou, Cheng-Tse Tang
  • Publication number: 20240371697
    Abstract: A method of the present disclosure includes forming a fin-shaped structure including a plurality of semiconductor layers, a first hard mask layer, a second hard mask layer, and a third hard mask layer, forming a patterned masking layer having a mask portion and a window portion, wherein the third hard mask layer is exposed through the window portion, performing a first etch process to expose the second hard mask layer through the window portion, performing a second etch process to etch the exposed second hard mask layer and to leave behind second hard mask layer residues, performing a third etch process to remove the second hard mask layer residues, etching the plurality of semiconductor layers in the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment, and forming an isolation feature around the first segment and the second segment.
    Type: Application
    Filed: July 11, 2024
    Publication date: November 7, 2024
    Inventors: Han-Yu Tsai, Zu-Yin Liu, You-Ting Lin, Jiun-Ming Kuo, Kuo-Chin Liu
  • Publication number: 20240368140
    Abstract: The present disclosure provides novel pladienolide compounds, pharmaceutical compositions containing such compounds, and methods for using the compounds as therapeutic agents. These compounds may be useful in the treatment of cancers, particularly cancers in which agents that target the spliceosome and mutations therein are known to be useful. Also provided herein are methods of treating cancers by administering at least one compound disclosed herein and at least one additional therapy.
    Type: Application
    Filed: February 20, 2024
    Publication date: November 7, 2024
    Applicant: EISAI R&D MANAGEMENT CO., LTD.
    Inventors: Gregg F. KEANEY, John WANG, Baudouin GERARD, Kenzo ARAI, Xiang LIU, Guo Zhu ZHENG, Kazunobu KIRA, Lisa A. MARCAURELLE, Marta NEVALAINEN, Ming-Hong HAO, Morgan Welzel O'SHEA, Parcharee TIVITMAHAISOON, Sudeep PRAJAPATI, Tuoping LUO, Nicholas C. GEARHART, Jason T. LOWE, Yoshihiko KOTAKE, Satoshi NAGAO, Regina Mikie KANADA SONOBE, Masayuki MIYANO, Norio MURAI, Andrew COOK, Shelby ELLERY, Atsushi ENDO, James PALACINO, Dominic REYNOLDS
  • Publication number: 20240368820
    Abstract: Laundry machines and methods for operating the same are disclosed. A laundry machine includes a container for containing laundry and a dehumidifier including a circulation fan for generating moist air flowing out of the container toward a moisture absorption and removal structure for absorbing moisture in the moist air, a regeneration fan for generating airflow including the moisture absorbed by the moisture absorption and removal structure to flow toward a condenser for condensing water from the generated airflow. The moisture absorption and removal structure is disposed adjacent to the circulation fan, the regeneration fan, and the condenser; wherein the moisture absorption and removal structure comprises a roller assembly, a functional roller is provided on at least one of a bottom portion of the roller assembly or a side of the roller assembly.
    Type: Application
    Filed: September 1, 2022
    Publication date: November 7, 2024
    Inventors: Xing LI, Chuanlin DUAN, Yadong YAN, Jibai HUANG, Zhimin YANG, Zhe WANG, Ming LIU, Chenghu LIN, Junjun FANG, Hang QI, Ming XU, Tong LIU, Gang QUAN