Abstract: An activation function generator based on a magnetic domain wall driven magnetic tunnel junction and a method for manufacturing the same are provided, including: a spin orbit coupling layer configured to generate a spin orbit torque; a ferromagnetic free layer formed on the spin orbit coupling layer and configured to provide a magnetic domain wall motion racetrack; a nonmagnetic barrier layer formed on the ferromagnetic free layer; a ferromagnetic reference layer formed on the nonmagnetic barrier layer; a top electrode formed on the ferromagnetic reference layer; antiferromagnetic pinning layers formed on two ends of the ferromagnetic free layer; a left electrode and a right electrode respectively formed at two positions on the antiferromagnetic pinning layers.

Abstract: A chip package includes an application chip, a micro-electromechanical systems (MEMS) chip, a conductive element, a bonding wire, and a molding compound. The application chip has a conductive pad. The MEMS chip is located on the application chip, and includes a main body and a cap. The main body is located between the cap and the application chip. The main body has a conductive pad. The conductive element is located on the conductive pad of the main body of the MEMS chip. The bonding wire extends from the conductive element to the conductive pad of the application chip. The molding compound is located on the application chip and surrounds the MEMS chip. The conductive element and the bonding wire are located in the molding compound.

Abstract: A method of forming a semiconductor structure includes the following operations. A semiconductor epitaxial layer is formed on a first semiconductor substrate. A first side of the semiconductor epitaxial layer is adhered to a transfer substrate by an adhesive layer covering the first side of the semiconductor epitaxial layer. The semiconductor epitaxial layer and the first semiconductor substrate are turned over by the transfer substrate. The first semiconductor substrate is removed to expose a second side of the semiconductor epitaxial layer opposite to the first side. A first semiconductor doped region is formed on the second side of the semiconductor epitaxial layer. After the first semiconductor doped region is formed, the adhesive layer and the transfer substrate are removed.

Abstract: A pyram-shaped deep-sea pressure-resistance shell and a design method therefor. The shell comprises a conical shell, an annular combined shell, a cylindrical shell, a flange bolt, and a perforated thick plate; a bottom end of the conical shell is connected with a top end of the annular combined shell, the conical shell being in communication with an interior part of the annular combined shell; the perforated thick plate blocks the bottom end of the annular combined shell, the perforated thick plate and the annular combined shell being connected by means of multiple flange bolts; the cylindrical shell is disposed inside the annular combined shell, a lower end of the cylindrical shell being inserted in a gap between the annular combined shell and the perforated thick plate.

Abstract: This application provides a resource indication method and apparatus, and relates to the field of communication technologies. In the method, the first communication apparatus may receive resource indication information. The resource indication information may include resource unit allocation information for indicating one or more first VRUs, and station information of a station to which the one or more first VRUs are allocated. There is a mapping relationship between the first PRU and the first VRU. The first communication apparatus transmits data on the first PRU.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.

Abstract: A dual-joint multi-degree-of-freedom mechanical arm and a driving method thereof. The mechanical arm comprises a base, a driving mechanism, a large arm module and a small arm module. The driving mechanism comprises three bidirectional driving components mounted on the base; and the big arm module comprises a big arm push rod, a big arm central rod and an elbow joint universal plate. The comprises a wrist joint universal plate, a universal joint coupler, a small arm central rod, a small arm stretching rod and a wrist joint universal plate. The small arm stretching rod comprises a first connecting rod and a second connecting rod in transmission connection. Two-degree-of-freedom rotation of the big arm module and the small arm module connected in series is independently realized by using three bidirectional driving components fixed on the base, so that movement flexibility of an end executor in a working space is greatly improved.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: A method includes generating quality of service requirement information which includes packet loss rate indication information. The packet loss rate indication information includes an acceptable maximum packet loss rate and a reference number of service data packets. The reference number of service data packets indicates a reference measurement number for counting the packet loss rate. The method also includes sending the quality of service requirement information.

Abstract: A staged cementing device includes a cylindrical body having an inner chamber. A circulating opening and a liquid inlet recess open to the inner chamber are arranged on a wall of the body. An opening assembly is arranged in the body, which has an opening sleeve and an opening seat located in the opening sleeve. Initially the opening sleeve is connected with the body through a first shear pin and covers the circulating opening, and the opening seat is connected with the opening sleeve through a second shear pin and covers the liquid inlet recess. A packer includes a packing valve body and a packer rubber. The packing valve body includes a flow channel in communication with the liquid inlet recess, and the packer rubber includes a liquid reservoir in communication with the flow channel. The second shear pin is sheared off in response to primary cementing procedure.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: A resonant vibration actuator is provided, comprising: a casing, a mover, a plurality of electromagnet sets, two elastic suspensions, and a connecting circuit; the casing is provided with connection terminals for connection on the outside; the mover comprising: a mover frame, a plurality of permanent magnet units, two magnetic backs, the permanent magnet units and the magnetic backs being arranged in the mover frame; the electromagnet sets being arranged between two permanent magnet units of the mover; the elastic suspensions being connected to the casing and the mover respectively through two connection portions at both ends; the connecting circuit being used to connect the electromagnet set and the connection terminals outside the casing; wherein, by energizing the electromagnet set, the electromagnet acts on the permanent magnet unit to make the mover move relatively in the casing to generate vibration.

Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.

Abstract: The present disclosure relates to laser treatment of an optical fiber to secure the optical fiber within a ferrule bore. In particular, the laser treatment modifies the physical structure of the optical fiber to aid in securing the optical fiber within the ferrule bore and to correct core-to-ferrule eccentricity errors.

Abstract: A new variable selective etching technology for thick SOI devices. An SOI material is etched by the following steps: (1) providing an SOI wafer; (2) depositing a composite hard mask with a variable selection ratio to replace a traditional hard mask with an invariable selection ratio; (3) applying a photoresist; (4) mask making, namely defining a to-be-etched region by using a photoetching plate; (5) etching the photoresist in the defined region; (6) etching the composite hard mask; (7) removing the photoresist; (8) etching top silicon by using a second etching method at a first selection ratio; and (9) etching a buried oxide layer by using a third etching method at a second selection ratio. The new variable selective etching technology avoids the damage to a side wall of a deep trench when the buried oxide layer is etched, and does not need to use an excessive thick hard mask.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes: a base substrate; a plurality of sub-pixels arranged on the base substrate, wherein the sub-pixels each include a sub-pixel driving circuit; a plurality of fingerprint recognition structures arranged on the base substrate, wherein the fingerprint recognition structures each include a control circuit and a fingerprint recognition electrode, the fingerprint recognition electrode is located on a side of the control circuit facing away from the base substrate, the control circuit is coupled to the fingerprint recognition electrode, and the control circuit is used for outputting a sensing signal from the fingerprint recognition electrode; wherein the control circuit and the sub-pixel driving circuit are arranged in a direction parallel to the base substrate.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: The present invention relates to a method for producing a protein hydrolysate using a polypeptide having endopeptidase activity and a polypeptide having carboxypeptidase activity and the use of these enzymes for hydrolysing a protein substrate. In addition, the present invention relates to polypeptides having carboxypeptidase activity and polynucleotides encoding the polypeptides. The invention also relates to nucleic acid constructs, vectors, and host cells comprising the polynucleotides as well as methods of producing and using the polypeptides.