Abstract: A semiconductor device having a transistor or capacitor with an ultra-thin oxide, which is thinner than 10 angstrom in thickness, is manufactured by eliminating a gate oxidation step in the processing and using the polysilicon reoxidation step to create the ultra-thin gate oxide by diffusion after formation of the gate.

Abstract: Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device is processed after the formation of the gates and gate oxides by N-type dopant implantation to form N-type shallow source and drain extension junctions. Spacers are formed for N-type dopant implantation to form N-type deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the NMOS source and drain extension junctions and junctions, and the spacers are removed. A thin oxide spacer is used to displace P-type dopant implantation to P-type shallow source and drain extension junctions. A nitride spacer is then formed for P-type dopant implantation to form P-type deep source and drain junctions. A second lower temperature rapid thermal anneal then independently optimizes the PMOS source and drain junctions independently from the NMOS source and drain junctions.

Abstract: A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process using a relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening. A reaction barrier layer is deposited between the gate dielectric with the high dielectric constant and the amorphous gate electrode material to prevent a reaction between the gate dielectric and the gate electrode material.

Abstract: A semiconductor device and a method of making the device with a raised source/drain has a semiconductive material that is non-selectively deposited in a layer over the device area. The semiconductive material is then etched to form spacers that will form the raised soure/drain areas following doping of the spacers. The gate of the semiconductor device is protected during the etching by an etch stop layer that is grown or deposited over the structure to be protected, e.g., the gate, prior to the deposition of the semiconductive material layer. Lightly doped drain ion implantation is performed prior to the formation of the spacers, and source-drain ion implantation is performed preferably after the formation of the spacers, to create the shallow junctions.

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract: Submicron contacts/vias and trenches are provided in a dielectric layer by forming an opening having an initial dimension and reducing the initial dimension by depositing a second dielectric material in the opening.

Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration.

Abstract: A method for ultra-fine patterning of a semiconductor device performs a first, anisotropic etching of a hard mask layer according to a pattern created by lithographic techniques to create lines in the hard mask layer having an initial width. A second, anisotropic etching is performed on the hard mask layer to narrow the lines further than otherwise possible with a single etching according to the patterns created by lithography. Using the narrowed lines created in the hard mask layer, a third, anisotropic etching is performed, this time on the conductor layer shadowed by the narrow lines of the hard mask layer. The third etching creates narrow lines in the conductor layer in accordance with the narrow lines of the hard mask layer.

Abstract: A novel semiconductor fabrication process having the advantages of conventional LOCOS (process simplicity and reduced defects) while providing a scaleable, planar isolation region between active regions formed in a semiconductor substrate. The preferred process includes formation of a barrier layer and a masking layer over the substrate. An active region mask defines an exposure region of the masking layer. The exposure region is etched to form an opening, exposing a portion of barrier layer in the opening. A spacer is added inside the opening, around a perimeter of the opening to define a second exposure region. The barrier layer, and substrate, under the second exposure region, but not under the spacer, are etched to form an isolation region opening. The isolation region opening may have a suitable isolating material, such as silicon oxide, grown, filled, or some combination of both, in the isolation region opening.

Abstract: A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.

Abstract: A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

Abstract: A method of fabricating a polysilicon gate 8 in a metal oxide semiconductor (MOS) transistor in an integrated circuit includes providing a metal layer 18, such as cobalt, on the sidewall 12 of the polysilicon gate 8, silicidizing the metal with the polysilicon in the polysilicon gate 8 to form a metal silicide sidewall 20, and removing the metal silicide sidewall 20 by etching.

Abstract: Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.

Abstract: A method for producing a small feature in a semiconductor device includes depositing a mask material on an unpatterned layer in which an ultra-narrow opening is to be formed, and then masking and etching the mask material to form a narrow opening. A spacer material is then deposited on the mask material, with spacer material settling into and covering the narrow opening. Thereafter, a portion of the spacer material is removed by etching, leaving some spacer material in the opening but exposing an ultra-narrow region of the first layer at the bottom of the opening in the mask material. The ultra-narrow region left uncovered by the spacer material is smaller than the narrow region in the mask material. Once the ultra-narrow region is uncovered, material in the first layer is removed through the ultra-narrow region, by anisotropic etching, for example, to form an ultra-narrow opening in the first layer.

Abstract: A method of manufacturing an MOS transistor having a gate length dimension less than the dimension available by methods available with conventional manufacturing methods that are limited by optical diffraction in photolithography. The method includes forming a polysilicon gate structure on a gate oxide layer, forming a nitrogen-doped layer on the polysilicon gate structure, forming selected depth oxide sidewalls on the polysilicon gate structure and etching the nitrogen-doped layer and the oxide sidewalls.

Abstract: Sub-micron contacts/vias and conductive lines in a dielectric layer are formed by etching through a photoresist mask containing openings having a dimension less than that achievable by conventional photolithographic techniques. Such minimal size openings are obtained by initially forming an oversized opening by conventional photolithographic techniques and then reducing the size of the opening by forming a sidewall spacer, such as a dielectric sidewall spacer, within the opening. In an embodiment, a plurality of openings are formed in first photoresist layer, each of which openings is provided with a sidewall spacer. The openings are filled with a filling material, such as a second photoresist material, and the photoresist mask and sidewall spacers are removed leaving a plurality of masking portions containing the second photoresist material. An underlying conductive layer is then etched through masking portions to form conductive lines having sub-micron dimensions.

Abstract: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings.

Abstract: A process is provided which enables electrical connection to be formed between gold and aluminum wires and copper interconnects. Conventional techniques for wire bonding are ineffective for bonding gold wires or aluminum wires to copper pads or copper interconnects. A process is provided to modify the copper pads so that conventional wire bonding techniques can be employed. In the process of the present invention an aluminum pad is formed over the copper interconnects. The metal wire is then bonded to the aluminum pad using conventional wire bonding techniques. No new hardware and/or technology is required for the metal wire bonding. No new technology is required to integrate the process of the invention into existing IC fabrication processes.

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.