Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.

Abstract: Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive substrate; a light sensing region on the semiconductive substrate; a waveguide region configured to guide light from a wave insert portion through a waveguide portion and to a sample holding portion; and an interconnect region below the waveguide region, and the interconnect region being disposed above the light sensing region. The waveguide portion includes a first dielectric layer comprising a first refractive index and at least one second dielectric layer comprising a second refractive index, wherein the second refractive index is smaller than the first refractive index.

Abstract: Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive substrate; a light sensing region on the semiconductive substrate; a waveguide region configured to guide light from a wave insert portion through a waveguide portion and to a sample holding portion; and an interconnect region below the waveguide region, and the interconnect region being disposed above the light sensing region. The waveguide portion includes a first dielectric layer comprising a first refractive index and at least one second dielectric layer comprising a second refractive index, wherein the second refractive index is smaller than the first refractive index.

Abstract: Some embodiments of the present disclosure provide an optical sensor. The optical sensor includes a semiconductive substrate. A light sensing region is on the semiconductive substrate. A waveguide region is configured to guide light from a wave insert portion through a waveguide portion and to a sample holding portion. The waveguide portion includes a first dielectric layer including a first refractive index. A second dielectric layer includes a second refractive index. The second refractive index is smaller than the first refractive index. A first interconnect portion is positioned in the waveguide portion, configured to transmit electrical signal from the light sensing region to an external circuit. The sample holding portion is over the light sensing region.

Abstract: A testing assembly for testing a magnetic sensor comprises a testing interface and a detachable magnetic-field generator. The testing interface has a base plate and plurality of testing terminals. The base plate has a first side and a second side opposite to the first side. The plurality of testing terminals is arranged on the first side of the base plate. The detachable magnetic-field generator is arranged on the second side of the base plate in a detachable fashion. The detachable magnetic-field generator has a coil support and at least one coil winding around the coil support.

Abstract: Some embodiments of the present disclosure, provide an optical sensor. The optical sensor includes a semiconductive substrate. A light sensing region is on the semiconductive substrate. A waveguide region is configured to guide light from a wave insert, portion through a waveguide portion and to a sample holding portion. The waveguide portion includes a first dielectric layer including a first refractive index. A second dielectric layer includes a second refractive index. The second refractive index is smaller than the first refractive index. A first interconnect portion is positioned in the waveguide portion, configured to transmit electrical signal from the light sensing region to an external circuit. The sample holding portion is over the light sensing region.

Abstract: A testing assembly for testing a magnetic sensor comprises a testing interface and a detachable magnetic-field generator. The testing interface has a base plate and plurality of testing terminals. The base plate has a first side and a second side opposite to the first side. The plurality of testing terminals is arranged on the first side of the base plate. The detachable magnetic-field generator is arranged on the second side of the base plate in a detachable fashion. The detachable magnetic-field generator has a coil support and at least one coil winding around the coil support.

Abstract: An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.

Abstract: A readout device is adapted for dual-band sensing, and includes an amplifier, two direct injection (DI) readout circuits to be respectively connected to two sensors, and a switching module. Through operation of the switching module, one of the DI readout circuits can be electrically connected to the amplifier, and cooperate with the other DI readout circuit to achieve a dual-band sensing feature.

Abstract: A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure.

Abstract: A readout device is adapted for dual-band sensing, and includes an amplifier, two direct injection (DI) readout circuits to be respectively connected to two sensors, and a switching module. Through operation of the switching module, one of the DI readout circuits can be electrically connected to the amplifier, and cooperate with the other DI readout circuit to achieve a dual-band sensing feature.

Abstract: A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.

Abstract: A readout device is adapted for dual-band sensing, and includes an amplifier, two direct injection (DI) readout circuits to be respectively connected to two sensors, and a switching module. Through operation of the switching module, one of the DI readout circuits can be electrically connected to the amplifier, and cooperate with the other DI readout circuit to achieve a dual-band sensing feature.

Abstract: A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 ?m and a depth of at least 5 ?m. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value.

Abstract: An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.

Abstract: A stacked integrated circuit system comprises a first chip with first average pattern density comprising memory cells, a second chip with second average pattern density comprising logic circuitries for the memory cells and a functioning unit and a plurality of through-silicon vias within one of the first chip and second chip to electrically connect the first chip and the second chip, wherein the memory cells of the first chip and the logic circuitries of the second chip are designed to be used collectively in order to perform complete memory functions, and wherein the first average pattern density is higher than the second average pattern density.

Abstract: A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.

Abstract: A semiconductor device comprises a substrate having a first side with a first surface and a second side with a second surface, a recessed through silicon via (TSV) penetrating the substrate and forming a first step height with respect to the first surface of the first side, a first extruded backside redistribution line (RDL) filling in the first step height and engaging with the recessed through silicon via.

Abstract: A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, a plurality of first interconnect structures, right above the TSV, configured for electrically coupling the TSV to a higher-level interconnect, a second interconnect structure traversing the TSV from the top and being configured for interconnect routing of an active device and a plurality of dummy metal patterns, right above the TSV, electrically isolated from the TSV, the first interconnect structures and the second interconnect structure.

Abstract: An integrated structure comprises a substrate with a first dielectric layer and a second dielectric cap layer disposed thereon in sequence, a metal gate transistor with a high-k gate dielectric layer on the substrate, a gate electrode embedded within the first dielectric layer and a source/drain within the substrate, a first metal contact penetrating the first dielectric layer and being in direct contact with the source/drain and a through-silicon via penetrating the second dielectric cap layer, the first dielectric layer and the substrate.