Patents by Inventor Ming-Sheng Yang

Ming-Sheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6461230
    Abstract: A method for changing the polishing selectivity ratio of slurry used in chemical-mechanical polishing. Barrier slurry and a diluent are mixed together at different ratios to produce a mixture containing different amounts of solvent, chemicals and polishing particles. Hence, a variety of polishing selectivity ratios between copper film or barrier layer and other materials is obtained. The mixture is transported to the polishing pad of a polishing station to carry out chemical-mechanical polishing.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: October 8, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Hsueh-Chung Chen, Ming-Sheng Yang
  • Publication number: 20020137360
    Abstract: The present invention provides a method for forming low dielectric constant layer in a semiconductor device comprising providing the semiconductor device. A polymer layer is formed on the semiconductor device, which has unsaturated carbon bonds compounds left after curing step. The polymer layer is then treated with ammonia-contained gas. The purpose of treatment of ammonia gas is to form and stabilize the polymer layer by saturating the unsaturated carbon bonds compounds in the polymer layer.
    Type: Application
    Filed: March 22, 2001
    Publication date: September 26, 2002
    Inventors: Cheng-Yuan Tsai, Ming-Sheng Yang
  • Patent number: 6455432
    Abstract: A method for removing carbon-rich particles adhered on a copper surface, especially on a copper surface of a copper/low k dielectric dual damascene structure is provided. A barrier layer and a barrier-CMP stopping layer are formed between the copper layer and the low k dielectric layer of the dual damascene structure. After a Cu-CMP process and a barrier CMP process, a chemical buffing polishing process using an acidic aqueous solution under a downward force of about 0.5 to 3 psi is performed to remove carbon-rich particles adhered on the exposed copper surface, which is due to the low k dielectric layer having at least 90% carbon element being exposed and then polished during the Cu-CMP process and the barrier CMP process, resulting from a dishing phenomenon of the copper layer occurring during the two CMP processes. Alternately, a first chemical buffing polishing process is followed after the Cu-CMP process, and a second chemical buffing polishing process is followed after the barrier CMP process.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: September 24, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chia-Lin Hsu, Yung-Tsung Wei, Ming-Sheng Yang
  • Publication number: 20020127874
    Abstract: A method of forming a low dielectric constant film. The low dielectric constant film is formed by passing gaseous silicate into a reaction chamber and performing a plasma chemical vapor deposition to form a carbon-rich layer. Micro-particles deposited on the dielectric film are purged by ammonia. By adjusting the flow rate of ammonia, and the pressure and plasma density inside the reaction chamber, several ammonium plasma conditions are produced in sequence to clear the particles on the dielectric film.
    Type: Application
    Filed: March 6, 2001
    Publication date: September 12, 2002
    Applicant: United Microelectronics Corp.
    Inventors: Neng-Hui Yang, Ming-Sheng Yang
  • Patent number: 6440861
    Abstract: A method of forming a dual damascene structure. A first dielectric layer and a second dielectric layer are sequentially formed over a substrate. A first photoresist layer is formed over the second dielectric layer. Photolithographic and etching operations are conducted to remove a portion of the second dielectric layer and the first dielectric layer so that a via opening is formed. A conformal third dielectric layer is coated over the surface of the second dielectric layer and the interior surface of the via opening. The conformal third dielectric layer forms a liner dielectric layer. A second photoresist layer is formed over the second dielectric layer and then the second photoresist layer is patterned. Using the patterned second photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned second photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: August 27, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Jui-Tsen Huang, Yi-Fang Cheng, Ming-Sheng Yang
  • Publication number: 20020115305
    Abstract: The present invention provides a method for stabilizing low dielectric constant materials in a semiconductor structure. The method comprises providing the semiconductor device and thereon spinning-on a dielectric layer. After curing step, the dielectric layer is treated with an aqueous solution, for example, containing ammonium hydroxide. With the aqueous solution, a passivated film formed on the suface of the dielectric layer, such as a polymer layer, can protect the dielectric layer from adsorption of moisture or solvents.
    Type: Application
    Filed: February 21, 2001
    Publication date: August 22, 2002
    Inventors: Cheng-Yuan Tsai, Yung-Tsung Wei, Teng-Chun Tsai, Ming-Sheng Yang
  • Patent number: 6429115
    Abstract: A method of manufacturing multilevel interconnects. A single or dual damascene interconnect structure is formed in a first dielectric layer. A cap layer or middle etch stop layer is formed over the interconnect structure and the first dielectric layer. The cap layer or the middle etch stop layer is treated with nitrogen plasma to convert a hydrophobic surface into a hydrophilic surface. An adhesion promoter layer is formed over the cap layer or middle etch stop layer. A low-k dielectric layer is formed over the adhesion promoter layer. A single or dual damascene structure is formed in the low-k dielectric layer, thereby forming a multilevel interconnect.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: August 6, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Tsai, Chin-Hsiang Lin, Ming-Sheng Yang
  • Patent number: 6429152
    Abstract: A method is given to form a thin film on a surface of a semiconductor wafer. The surface has at least a first region, containing an inner portion of the wafer, and a second region, containing an outer portion of the wafer, and slopes outward from the first region to the second region. The method starts with performing an in-situ inert gas plasma treatment on the surface of the semiconductor wafer to generate different temperatures from the first region to the second region. Different deposition rates of a precursor A from the first region to the second region are thus generated so as to form a flat surface. Then a precursor A-chemical vapor deposition (CVD) process is performed to form the thin film with the flat surface immediately after performing the inert gas plasma treatment.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: August 6, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Hui Yang, Ming-Sheng Yang
  • Publication number: 20020102840
    Abstract: The present invention provides a method to form a copper interconnect and avoid a dishing phenomenon on the copper interconnect in the manufacturing process which will cause the metal line thinning and high resistance. By using a cap layer selectively positioned over the dual damascene structure, the method can balance the difference of polishing rate between the copper and the surrounding material. Such we can get a plane surface of interconnect in a chemical mechanical polishing process.
    Type: Application
    Filed: January 31, 2001
    Publication date: August 1, 2002
    Inventors: Teng-Chun Tsai, Chai-Lin Hsu, Yung-Tsung Wei, Ming-Sheng Yang
  • Publication number: 20020090893
    Abstract: This invention relates to a method for improving curvature of the polished surface by chemical mechanical polishing comprising a polishing table, a polishing pad, a polishing head and a slurry exhaust system. The polishing head comprises a revolving spindle and the slurry exhaust system comprises a slurry outlet. The method for improving curve rate of the polished surface by chemical mechanical polishing is in order to make the slurry distributing on the polishing pad non-uniformly in controlling to control removing rate on each point of the polishing surface by the concentration of the slurry. This method will improve the defects in non-smooth on the wafer-polishing surface to make the wafer-polishing surface in full flatness after polishing.
    Type: Application
    Filed: January 8, 2001
    Publication date: July 11, 2002
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Hsu, Teng-Chun Tsai, Yung-Tsung Wei, Ming-Sheng Yang
  • Patent number: 6410446
    Abstract: A method of filling a gap is proposed. The method of the invention is applied on a substrate which has conductive structures formed thereon. A HDPCVD is performed to form a dielectric layer on the substrate. The HDPCVD process comprises multi-steps. In a first step, a gas source is added to a deposition chamber to form dielectric material over the substrate. The gas source comprises reactive gas and inert gas. Thus, the first step can simultaneously perform deposition and sputtering. In a second step, the reactive gas is driven out of the deposition chamber. Only sputtering is used to remove a part of the dielectric material at top corners of the conductive structures. In a third step, the reactive gas is again added into the deposition chamber to deposit the dielectric material until filling the gap.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: June 25, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Tsai, Chih-Chien Liu, Ming-Sheng Yang
  • Patent number: 6410106
    Abstract: A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: June 25, 2002
    Assignee: United Microelectronics Crop.
    Inventors: Cheng-Yuan Tsai, Chih-Chien Liu, Ming-Sheng Yang
  • Patent number: 6406978
    Abstract: A method of removing silicon carbide. A silicon wafer is used as a dummy wafer for inspecting the properties of a silicon carbide thin film which is to be formed thereover. A silicon nitride layer with a thickness larger than about 1000 angstroms is formed on the dummy wafer as a base layer of the silicon carbid thin film. The silicon carbide thin film is then formed on the base layer. The property inspection of the silicon carbide thin film is performed. After the properties inspection, the silicon carbide is stripped using a high density hydrogen plasma. After the step of high density hydrogen plasma, if the remaining silicon nitride layer is thicker than about 500 angstroms, the remaining silicon nitride layer can be used as the base layer again for forming and inspecting the properties of the silicon carbide thin film.
    Type: Grant
    Filed: November 18, 2000
    Date of Patent: June 18, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Hui Yang, Ming-Sheng Yang, Chien-Mei Wang
  • Patent number: 6403469
    Abstract: A method of producing a dual damascene structure. A substrate is provided and an insulation layer is formed over the substrate. A dual damascene opening is formed in the insulation layer. A liner layer is formed over the exposed surface of the dual damascene opening. Metallic material is deposited over the substrate filling the dual damascene opening to form a metallic layer. A cap layer is formed over the metallic layer. A chemical-mechanical polishing operation is carried out to polish the cap layer using a metal-reactive solution or a cap-layer-reactive solution. The polishing operation continues until the cap layer outside the dual damascene opening is completely removed and the metallic layer is exposed. A portion of the cap layer remains above the dual damascene opening. Using the retained cap layer as a protective layer for the metallic layer, the metallic layer outside the dual damascene opening is removed by polishing until the liner layer is exposed.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: June 11, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Hsueh-Chung Chen, Ming-Sheng Yang
  • Publication number: 20020068435
    Abstract: A method for removing carbon-rich particles adhered on the exposed copper surface of a copper/low k dielectric dual damascene structure is provided. A barrier layer and a barrier-CMP stopping layer are formed between the copper layer and the low k dielectric layer of the dual damascene structure. After a Cu-CMP process and a barrier CMP process are completed, a chemical buffing polishing process using a basic solution under a downward force of about 0.5 to 3 psi is performed to remove carbon-rich particles adhered on the exposed copper surface due to the low k dielectric having at least 90% carbon element being exposed and then polished during the Cu-CMP process and the barrier CMP process, which results from a dishing phenomenon of the copper layer occurring during the two CMP processes. Finally, a post chemical mechanical polishing cleaning process is performed to remove away dirt left on the exposed copper surface.
    Type: Application
    Filed: December 5, 2000
    Publication date: June 6, 2002
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Teng-Chun Tsai, Chia-Lin Hsu, Yung-Tsung Wei, Ming-Sheng Yang
  • Publication number: 20020068455
    Abstract: A method for removing carbon-rich particles adhered on a copper surface, especially on a copper surface of a copper/low k dielectric dual damascene structure is provided. A barrier layer and a barrier-CMP stopping layer are formed between the copper layer and the low k dielectric layer of the dual damascene structure. After a Cu-CMP process and a barrier CMP process, a chemical buffing polishing process using an acidic aqueous solution under a downward force of about 0.5 to 3 psi is performed to remove carbon-rich particles adhered on the exposed copper surface, which is due to the low k dielectric layer having at least 90% carbon element being exposed and then polished during the Cu-CMP process and the barrier CMP process, resulting from a dishing phenomenon of the copper layer occurring during the two CMP processes. Alternately, a first chemical buffing polishing process is followed after the Cu-CMP process, and a second chemical buffing polishing process is followed after the barrier CMP process.
    Type: Application
    Filed: December 5, 2000
    Publication date: June 6, 2002
    Applicant: United Microelectronics Corp.
    Inventors: Teng-Chun Tsai, Chia-Lin Hsu, Yung-Tsung Wei, Ming-Sheng Yang
  • Publication number: 20020065025
    Abstract: A chemical-mechanical polishing method for polishing a copper oxide layer and a copper layer. The copper oxide layer above the copper layer is first polished using an aqueous solution having a high concentration of polishing particles/chelating agent. The copper layer is then polished using a polishing slurry having a low concentration of polishing particles/chelating agent or the polishing slurry free of polishing particles/chelating agent. Alternatively, the copper oxide layer is polished using a mixture of the aqueous solution and the polishing slurry. After the copper oxide layer is removed, the copper layer is polished using the polishing slurry alone.
    Type: Application
    Filed: December 12, 2000
    Publication date: May 30, 2002
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Lin Hsu, Teng-Chun Tsai, Yung-Tsung Wei, Ming-Sheng Yang
  • Patent number: 6387813
    Abstract: A method for stripping a low dielectric film with a high carbon content from silicon monitor chip. The silicon monitor chip is placed inside a plasma-enhanced chemical vapor deposition chamber and the surface is treated with oxygen plasma to form a silicon-rich oxide layer. A high-carbon-content low dielectric film is formed over the silicon-rich oxide for film quality inspection. After the film inspection, the silicon monitor chip is immersed in a solution containing ammonium hydroxide and hydrogen peroxide so that the surface of the high-carbon-content dielectric film is transformed from hydrophobic to hydrophilic. Hence, wetting capacity of subsequently applied hydrofluoric acid solution is enhanced. Finally, the silicon monitor chip is immersed in a hydrofluoric acid solution for stripping away the low dielectric film.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: May 14, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Hui Yang, Ming-Sheng Yang, Chih-Chien Liu
  • Patent number: 6383913
    Abstract: A method for improving surface wettability of inorganic low dielectric material is disclosed. The method includes an inorganic dielectric material as a low-k dielectric barrier layer is spun-on the semiconductor device. Then, inorganic dielectric material surface is treated by ultraviolet (UV) treatment that the surface characteristic of inorganic dielectric material is changed from hydrophobic to hydrophilic. Thus, the surface wettability of inorganic dielectric material can be improved and adhesion ability between the inorganic dielectric material and organic polymer can be increased.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: May 7, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Tsai, Ming-Sheng Yang
  • Patent number: 6380069
    Abstract: A method of removing the micro-scratches on a metal layer is described, wherein the metal layer is formed on a barrier layer conformally onto a dielectric layer having a hole thereon, and wherein the metal layer over-fills the hole. The method comprises three chemical-mechanical polishing steps as described hereinbelow. The first chemical-mechanical polishing step is that oxidizing and polishing away the metal layer outside the hole, with a first slurry, wherein the first slurry has a chemical solution and has a plurality of abrasive particles. The second chemical-mechanical polishing step is that polishing away the barrier layer outside the hole, with a second slurry, whereby a plurality of micro-scratches are formed on the metal layer after the barrier layer is chemical-mechanically polished. The third chemical-mechanical polishing step is that buffing the metal layer, with the first slurry, thereby removing the micro-scratches on the metal layer.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: April 30, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Hsueh-Chung Chen, Yung-Tsung Wei, Ming-Sheng Yang