Patents by Inventor Ming-Sheng Yang

Ming-Sheng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6376394
    Abstract: A fabrication method for an inter-metal dielectric layer is applicable to multi-level interconnects. A substrate is provided with metal lines formed thereon. A first (fluorinated silicon glass) FSG layer with low fluorine content is then formed on the substrate, followed by forming a biased-clamped FSG layer on the first FSG layer. A second FSG layer with low fluorine content is formed on the biased-clamped layer, prior to forming an oxide cap layer on the second FSG layer. The oxide cap layer is planarized until the oxide cap layer is level with the second FSG layer.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: April 23, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Tsai, Chih-Chien Liu, Ming-Sheng Yang
  • Patent number: 6365527
    Abstract: A silicon carbide film is formed in a manner which avoids the high level contents of oxygen by depositing the film in at least two consecutive in-situ steps. Each step comprises plasma enhanced chemical vapor deposition (PECVD) of silicon carbride and ammonia plasma treatment to remove oxygen contained in the deposit silicon carbide. The disclosed method is found to enhance several insulation properties of the silicon carbide film and can be easily adapted into production-level IC processing.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: April 2, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Hui Yang, Ming-Sheng Yang
  • Patent number: 6365228
    Abstract: A process for spin-on coating with an organic material having a low dielectric constant, which is suitable for a substrate. A dielectric base layer capable of protecting metal is formed on the substrate, an adhesive promoter layer is formed on the dielectric base layer, and the adhesive promoter layer is baked. A solvent is then used to clean the substrate and simultaneously to dissolve a part of the adhesive promoter layer in order to flatten the adhesive promoter layer. Afterwards, a layer of an organic material with a low dielectric constant is spin-on coated on the adhesive promoter layer, and the layer of an organic material with a low dielectric constant is baked and cured.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: April 2, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Tsai, Ming-Sheng Yang, Chin-Hsiang Lin
  • Patent number: 6362101
    Abstract: A method for chemical mechanical polishing a component includes providing an oxide layer and forming at least one via through the oxide layer. A tungsten layer is formed within the via and over the oxide layer. A first chemical mechanical polishing step is carried out on a polishing pad using a first slurry having an oxidizing component and having a pH of approximately 2 to approximately 4 to remove the tungsten layer from over the oxide layer. A second chemical mechanical polishing step is carried out on the polishing pad using a second slurry having a pH of approximately 2 to approximately 4 to polish scratches out of the oxide layer.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: March 26, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Sheng Yang, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
  • Publication number: 20020025689
    Abstract: A chemical-mechanical polishing method utilizes a shallow dummy pattern for planarizing a dielectric layer. The method includes the steps of first forming a shallow dummy pattern on the dielectric layer, and then coating a patterned photoresist layer over the dielectric layer. Thereafter, the photoresist layer is used as a mask to form openings in other areas of the dielectric layer. Subsequently, the photoresist layer is removed to expose the shallow dummy pattern, and then a glue/barrier layer and a conductive layer are sequentially deposited. Next, a chemical-mechanical polishing operation is carried out to remove excess conductive layer and glue/barrier layer above the dielectric layer as well as the shallow dummy pattern at the same time. Since the removal rate of glue/barrier layer in each area above the dielectric layer is about the same, a planar substrate surface is obtained.
    Type: Application
    Filed: February 20, 2001
    Publication date: February 28, 2002
    Inventors: Ming-Sheng Yang, Yimin Huang, Juan-Yuan Wu, Water Lur
  • Patent number: 6344408
    Abstract: A method for improving non-uniformity of chemical mechanical polishing by over coating layer is disclosed. The essential point of the invention is that an over coating layer is formed over a surface before the surface is planarized by a chemical mechanical polishing process. Note that polishing rate of the over coating layer must be less than the polishing rate of the surface, where the ratio of polishing rate is called as selectivity. Because the topography of the surface is not uniform, the topography of the over coating layer also is non-uniform and then the polishing probability in different parts of the over coating layer is different. Obviously, when the over coating layer on the higher area part of the surface is totally consumed, these are residual over coating layer on the lower area part of the surface. Thus, over polishing in the lower area part is prevented by residual over coating layer.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: February 5, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Hsueh-Chung Chen, Ming-Sheng Yang, Juan-Yuan Wu, Water Lur
  • Patent number: 6323123
    Abstract: A barrier layer is formed over the substrate by deposition, and a first dielectric is formed over the diffusion barrier layer by deposition. A etching stop layer and a second dielectric are formed in turn over the first dielectric by deposition. Next, a hard mask is formed on the second dielectric. Then, a photoresist layer is formed over the hard mask, and defining the photoresist layer. And then dry etching is carried out by means of the photoresist layer as the mask to form a via hole. A gap-filling material is filled on the second dielectric and into the via hole by conventional partial-cured (or un-cured) spin-on glass method. A anti-reflection layer is formed over the second dielectric by deposition. Another photoresist layer is formed on the anti-reflection coating and defined the photoresist layer, and to expose the partial surface of the via hole and the anti-reflection coating.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: November 27, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Cheng-Yuan Tsai, Anseime Chen, Ming-Sheng Yang
  • Patent number: 6306757
    Abstract: A metallization method for forming multilevel interconnect is disclosed. The method includes firstly providing a first conductor layer on which there is a dielectric layer. A glue layer is then formed on the dielectric layer, followed by forming an opening from top surface of the glue layer to the first conductor layer. After forming a barrier layer on the glue layer and all surfaces in the opening, a second conductor is formed on the barrier layer and fills the opening. Subsequently, the second conductor layer and the barrier layer are removed until the glue layer exposes. A third conductor is defined on the glue layer and the second conductor. The product will solve the problem of high via resistivity caused by stripping solvent and etchant.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: October 23, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Keh-Ching Huang, Ming-Sheng Yang, Tong-Yu Chen, Tzu-Guey Jung
  • Patent number: 6280079
    Abstract: A slurry mixing apparatus has a mixing chamber, a rotatable bearing and several blades. The bearing is connected to one end of each of the blades and located in the center of the mixing chamber. Several kinds of the slurries can be mixed rapidly in the apparatus and flowed into the CMP polisher immediately to perform a CMP process. Being mixed by the mixing chamber, the slurry is supplied to the chemical mechanical polisher for polishing.
    Type: Grant
    Filed: December 24, 1998
    Date of Patent: August 28, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Sheng Yang, Peng-Yih Peng, Chia-Jui Chang, Juan-Yuan Wu
  • Publication number: 20010002335
    Abstract: A method for chemical mechanical polishing a component includes providing an oxide layer and forming at least one via through the oxide layer. A tungsten layer is formed within the via and over the oxide layer. A first chemical mechanical polishing step is carried out on a polishing pad using a first slurry having an oxidizing component and having a pH of approximately 2 to approximately 4 to remove the tungsten layer from over the oxide layer. A second chemical mechanical polishing step is carried out on the polishing pad using a second slurry having a pH of approximately 2 to approximately 4 to polish scratches out of the oxide layer.
    Type: Application
    Filed: November 24, 1997
    Publication date: May 31, 2001
    Inventors: MING-SHENG YANG, JUAN-YUAN WU, WATER LUR, SHIH-WEI SUN
  • Publication number: 20010001678
    Abstract: A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.
    Type: Application
    Filed: January 11, 2001
    Publication date: May 24, 2001
    Inventors: Cheng-Yuan Tsai, Chih-chien Liu, Ming-Sheng Yang
  • Patent number: 6214745
    Abstract: A chemical-mechanical polishing method utilizes a shallow dummy pattern for planarizing a dielectric layer. The method includes the steps of first forming a shallow dummy pattern on the dielectric layer, and then coating a patterned photoresist layer over the dielectric layer. Thereafter, the photoresist layer is used as a mask to form openings in other areas of the dielectric layer. Subsequently, the photoresist layer is removed to expose the shallow dummy pattern, and then a glue/barrier layer and a conductive layer are sequentially deposited. Next, a chemical-mechanical polishing operation is carried out to remove excess conductive layer and glue/barrier layer above the dielectric layer as well as the shallow dummy pattern at the same time. Since the removal rate of glue/barrier layer in each area above the dielectric layer is about the same, a planar substrate surface is obtained.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: April 10, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Sheng Yang, Yimin Huang, Juan-Yuan Wu, Water Lur
  • Patent number: 6210256
    Abstract: A continuous pad feeding method for chemical-mechanical polishing (CMP) is described, which method is suitable for use in a CMP apparatus. The CMP apparatus includes a first polishing belt having two terminals, which first polishing belt serves as a plurality of polishing pads. A second polishing belt having two terminals is provided on the first polishing belt. One of the terminals of the second polishing belt is adhered to one of the terminals of the first polishing belt.
    Type: Grant
    Filed: December 31, 1999
    Date of Patent: April 3, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Hsueh-Chung Chen, Wen-Cheng Yeh, Ming-Sheng Yang
  • Patent number: 6200653
    Abstract: A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: March 13, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan Tsai, Chih-Chien Liu, Ming-Sheng Yang
  • Patent number: 6197681
    Abstract: A method for forming the copper interconnects is disclosed. The method includes, firstly, providing a semiconductor substrate is provided. Then, a first dielectric layer is formed. Sequentially, a second dielectric layer is formed and an anti-reflective layer is formed. Then, a hardmask layer is formed. Etching of the hardmask layer is carried out. The photoresist layer is removed and another photoresist is replaced. The anti-reflective layer, the second dielectric layer and the first dielectric layer are all etched. The hardmask layer, the anti-reflective layer and the second dielectric layer are all etched. The photoresist layer, the hardmask layer and the anti-reflective layer are all removed. A first barrier layer is conformably formed on the sidewalls and the exposed surfaces of the second dielectric layer and the first dielectric layer, and on the surface of the first copper layer. A seed layer is conformably formed on the barrier layer.
    Type: Grant
    Filed: December 31, 1999
    Date of Patent: March 6, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Cheng-Yuan Tsai, Ming-Sheng Yang
  • Patent number: 6169028
    Abstract: A method for fabricating a metal interconnect structure. A semiconductor substrate comprising a conductive layer therein is provided. A dielectric layer is formed on the semiconductor substrate. A part of the dielectric layer is removed to form a dual damascene opening and a trench therein, wherein the dual damascene opening exposes the conductive layer. The trench is larger than the dual damascene opening. A conformal barrier layer is formed on the dielectric layer. A conformal metal layer is formed on the barrier layer to fill the dual damascene opening and to partially fill the trench. The metal layer positioned in the trench has a thickness equal to the depth of the trench. A conformal cap layer is formed on the metal layer. A CMP process is performed to remove the cap layer, the metal layer and the barrier layer outside the trench and outside the dual damascene opening.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: January 2, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Chih Wang, Ming-Sheng Yang, Wen-Yi Hsieh
  • Patent number: 6155912
    Abstract: The present invention provides a cleaning solution for cleaning a polishing pad used in a chemical-mechanical polishing (CMP) process for polishing the surface of a semiconductor wafer. The cleaning solution comprises a potassium hydroxide (KOH) solution for cleaning off slurry remaining on the surface of the polishing pad, and a hydrogen peroxide (H.sub.2 O.sub.2) solution and ammonia water (NH.sub.4 OH) solution for removing abrasive debris remaining on the surface of the polishing pad after the chemical-mechanical polishing process.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: December 5, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Hsueh-Chung Chen, Ming-Sheng Yang, Juan-Yuan Wu
  • Patent number: 6077147
    Abstract: A chemical-mechanical polishing station for polishing wafers. The polishing station comprises a slurry supplier, a polishing pad capable of collecting the slurry, and a polishing head capable of rotating a wafer and lowering the wafer onto the polishing pad in contact with the polishing pad and the slurry during a polishing session. The polishing head further includes a retaining ring for positioning the wafer. The retaining ring houses a light-emitting device capable of shining a beam of light onto the slurry and a light sensor for picking up the beam of light reflected back from the slurry. The exact polishing end-point can be decided by analyzing signals obtained from the light sensor.
    Type: Grant
    Filed: June 19, 1999
    Date of Patent: June 20, 2000
    Assignee: United Microelectronics Corporation
    Inventors: Ming-Sheng Yang, Hsueh-Chung Chen, Tsang-Jung Lin, Juan-Yuan Wu
  • Patent number: 6062964
    Abstract: A chemical mechanical polishing apparatus for controlling slurry distribution is disclosed. The slurry flowing through the mesh before transferring to the polishing pad, the mesh being used to distribute the slurry onto surface of the polishing pad. There are different netting densities over the mesh, achieving the purpose of controlling slurry distribution.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: May 16, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Hsueh-Chung Chen, Ming-Sheng Yang, Juan-Yuan Wu
  • Patent number: 6036356
    Abstract: An in-situ CMP slurry mixing apparatus. The apparatus comprises a tubular main body and a plurality of tapered plugs. The tubular main body further comprises a plurality of first tubes with a first diameter, a plurality of second tubes with a second diameter. Each tapered plug is placed in each second tube, the tips of each tapered plug are pointed in the same direction, and the tips are each oriented opposite to a flowing direction of a CMP slurry. In addition, the second diameter is larger than the first diameter, and a diameter of the base of each tapered plug is larger than the first diameter but is smaller than the second diameter.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: March 14, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Sheng Yang, Chien-Hsin Lai, Chia-Jui Chang, Juan-Yuan Wu