Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

Abstract: 9An improved electro-chemical deposition copper (ECD-Cu) apparatus and a method of preventing cavities in an ECD-Cu thin film are provided. The electro-chemical deposition apparatus has a bath tank, an anode positioned in the bath tank, and a spin plate for positioning a semiconductor wafer that is used as a cathode. The method, by alternating a spin direction of the spin plate between a clockwise direction and a counterclockwise direction, every 1 to 10 seconds, prevents an electrolyte solution of the bath tank from forming a stable vortex, and suppresses a phenomenon of forming cavities in the ECD-Cu thin film when bubbles of the vortex adhere to the wafer surface.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

Abstract: The present invention disclosed a method for manufacturing a semiconductor device on a semiconductor substrate, the method comprising the steps of: forming a gate dielectric layer on the semiconductor substrate. A gate is formed on the gate dielectric layer. A first ion implantation is performed to form extended source and drain shallow junctions in the semiconductor substrate. Spacer are formed on the side wall of the gate with liner between the gate and the spacers. The source and drain region is formed by performing a second ion implantation. A thermal annealing is used to eliminate the implantation defect and active the dopants. A surface treatment is used to form selective polycrystalline silicon on the gate and the source and drain region, thereby forming raised source and drain. A Cobalt layer is formed on the selective polycrystalline silicon.

Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with either damascene or conventional integrated circuit metallization schemes. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Abstract: An air gap structure and formation method for substantially reducing capacitance in a dual damascene based interconnect structure is disclosed. The air gap extends above, and may also additionally extend below, the damascene interconnects desired to be isolated thus minimizing fringing fields between the lines. Multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels.

Abstract: A gate oxide layer and a gate are sequentially formed on a substrate, and a source/drain extension is formed in the substrate thereafter. A liner layer is then formed to cover the substrate, and a first dielectric layer and a second dielectric layer are sequentially formed on the liner layer. By performing an etching process, a L-shaped spacer is formed on either side of the gate. Portions of the liner layer uncovered by the L-shaped spacer are then removed, and a step source/drain extension and a source/drain are simultaneously formed in the substrate thereafter. Finally, a salicide process is performed to form a silicide layer on the gate and on portions of the silicon substrate surface above the source/drain.

Abstract: In the normal fabrication of copper interconnects process, after electro copper deposition (ECD), small copper grains are formed on the surface of copper and the initial grain growth of copper grain is not stable enough and it will grow up in the subsequent unavoidable thermal treatments. Currently, long time low temperature thermal process by furnace is usually adopted to produce a better initial grain growth after electro copper deposition (ECD). However, this long time low temperature thermal process is usually not good enough to stabilize the copper grain in dual damascene structure. In this invention, a fabrication process by adding an extra thermal treatment of short time high temperature processes is used to saturate copper grain growth in copper via holes. By doing this extra thermal step, the internal stress of copper becomes stable than the stress of that after the long time low temperature thermal treatment. The internal structure of copper will thus attain a more stable stress.

Abstract: A first dielectric layer 310 is formed on a substrate, wherein the first dielectric layer is a low-K material of an organic polymer. An adhesion promoter is then deposited on the first dielectric layer by chemical vapor deposition to form a first interlayer, wherein the first adhesion promoter is an organic material that comprises a C—H group and a siloxane (Si—O), such as methyltriacetoxysilane (MTAS). Next, an inorganic layer is formed on the first interlayer. Then the adhesion promoter mentioned previously is deposited on the inorganic layer by chemical vapor deposition to form a second interlayer. Next, a second dielectric layer is formed on the second interlayer 340, wherein the second interlayer is a low-K material of an organic polymer. Finally, a baking process is performed.

Abstract: A chemical-mechanical polishing method for polishing a copper oxide layer and a copper layer. The copper oxide layer above the copper layer is first polished using an aqueous solution having a high concentration of polishing particles/chelating agent. The copper layer is then polished using a polishing slurry having a low concentration of polishing particles/chelating agent or the polishing slurry free of polishing particles/chelating agent. Alternatively, the copper oxide layer is polished using a mixture of the aqueous solution and the polishing slurry. After the copper oxide layer is removed, the copper layer is polished using the polishing slurry alone.

Abstract: A polarization method that utilizes a chemical-mechanical polishing operation. In the polishing operation, slurry for polishing a metallic layer is first employed to remove a greater portion of the metallic layer. Next, slurry for polishing a dielectric layer and having properties very similar to the metal-polishing slurry is added and mixed together with the slurry for polishing a metallic layer so that the polishing rate for the dielectric layer is increased. Consequently, metallic residues remaining on the dielectric layer are removed and a planar dielectric layer is obtained at the same time.

Abstract: A gate oxide layer and a gate are sequentially formed on a substrate, and a source/drain extension is formed in the substrate thereafter. A liner layer is then formed to cover the substrate, and a first dielectric layer and a second dielectric layer are sequentially formed on the liner layer. By performing an etching process, a L-shaped spacer is formed on either side of the gate. Portions of the liner layer uncovered by the L-shaped spacer are then removed, and a step source/drain extension and a source/drain are simultaneously formed in the substrate thereafter. Finally, a salicide process is performed to form a silicide layer on the gate and on portions of the silicon substrate surface above the source/drain.

Abstract: A method of forming a low dielectric constant film. The low dielectric constant film is formed by passing gaseous silane into a reaction chamber and performing a plasma chemical vapor deposition to form a carbon-rich layer. Micro-particles deposited on the dielectric film are purged by ammonia. By adjusting the flow rate of ammonia, and the pressure and plasma density inside the reaction chamber, several ammonium plasma conditions are produced in sequence to clear the particles on the dielectric film.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor structure and forming a first dielectric layer on the semiconductor structure. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etching mask. A second dielectric layer is formed between the conductor structures, which has a dielectric constant smaller than the first dielectric layer. The second dielectric layer also alternatively has air voids contained therein to reduce dielectric constants.

Abstract: A planarization method that utilizes a chemical-mechanical polishing operation. In the polishing operation, a first slurry for polishing a metallic layer is first employed to remove a greater portion of the metallic layer. Next, a second slurry for polishing a dielectric layer and having properties very similar to the metal-polishing slurry is added and mixed together with the slurry for polishing a metallic layer so that the polishing rate for the dielectric layer is increased. Consequently, metallic residues remaining on the dielectric layer are removed, and a planar dielectric layer is obtained at the same time.

Abstract: A method of densifying a superficial layer on a low dielectric constant film. A substrate is provided. A low dielectric constant material layer is formed over the substrate. An inert gas plasma treatment of the low dielectric constant material layer is conducted so that a superficial layer of the low dielectric constant material layer is densified into a protective layer. The protective layer protects the low dielectric constant material layer against attacks by plasma and chemicals during subsequent processes and prevents any deterioration of electrical properties.

Abstract: The present invention provides a method for electroplating. A substrate is provided with an opening and a metal layer is formed over the substrate and fills the opening. A cleaning solution including benzotriazole is used to clean the surface of the metal layer, while a protective layer is formed on the surface of the metal layer from reactions of benzotriazole with metal.

Abstract: The present invention provides a method for stabilizing low dielectric constant materials in a semiconductor structure. The method comprises providing the semiconductor structure and thereon spinning-on a dielectric layer. After a curing step, the dielectric layer is treated with an aqueous solution containing, for example, ammonium hydroxide. With the aqueous solution, a passivated film formed on the surface of the dielectric layer, such as a polymer layer, can protect the dielectric layer from adsorption of moisture or solvents.