Abstract: In some embodiments, laser devices having contact pads are formed. The laser diodes are formed from a doped semiconductive material. The contact pads and semiconductive material share an ohmic junction. Underbump metallurgies are formed on the contact pads. Conductive connectors are electrically coupled to the laser devices. The underbump metallurgies help prevent metal inter-diffusion between the contact pads and conductive connectors. As such, when reflowing the conductive connectors, the junction of the contact pads and semiconductive material may retain its ohmic properties.

Abstract: An advanced semiconductor packaging structure includes a circuit board, a first chip disposed on the circuit board, and a second chip disposed on the first chip. The first chip has solder balls arranged at intervals and bonded to the circuit board, and first pads arranged at intervals. The second chip has second pads arranged at intervals. Each of the second pads is correspondingly bonded to each of the first pads. Each of the first and second pads comprises a graphene-copper composite material composed of graphene and copper. The graphene has a plurality of graphene microfilms. The graphene microfilms are dispersed and arranged in the gaps between adjacent copper atoms. The graphene microfilms have covalent bonds. Based on the total weight of the graphene-copper composite material, the graphene content is less than 3 wt %, and the oxygen content in the graphene-copper composite material is not greater than 10 ppm.

Abstract: A semiconductor device includes a substrate, an ILD layer on the substrate, a contact electrode unit with a gate wiring layer and contacts in the ILD layer, a lower IMD layer on the ILD layer, a wiring unit with lower and upper wiring layers disposed on the lower IMD layer and connected to the contacts, interconnect units stacked along a height direction on the wiring unit, including an upper IMD layer, lower and upper wiring layers and interconnects in the upper IMD layer and connected to each other; and a bonding pad unit including an insulating layer, interconnects and an upper wiring layer in the insulating layer connected to each other. The lower wiring layer is made of a graphene-copper composite material having graphene flakes covalently bonded and dispersed between copper atoms. The graphene content is less than 3 wt % and the oxygen content is no more than 10 ppm.

Abstract: A method comprises cleaning a surface of a reticle by irradiating the surface of the reticle in a first exposure device for a predetermined irradiation time. A layout pattern of the reticle is projected onto a photo resist layer of a wafer in a second exposure device by an EUV radiation. The photo resist layer is developed to generate a photo resist pattern on the wafer. A surface of the wafer is imaged to generate an image of the photo resist pattern on the wafer. The generated image of the photo resist pattern is analyzed to determine critical dimension uniformity (CDU) of the photo resist pattern. The predetermined irradiation time is adjusted until the determined CDU satisfies a predetermined criterion.

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Abstract: A method of manufacturing a semiconductor device includes the following steps. A semiconductor substrate is provided. A plurality of dielectric layers and a plurality of first conductive features in the dielectric layers are formed on the semiconductor substrate. At least one polymer layer and a plurality of second conductive features in the at least one polymer layer on the dielectric layers are formed. A plurality of conductive connectors are formed to electrically connect to the second conductive features. The semiconductor substrate, the dielectric layers and the at least one polymer layer are cut into a plurality of dies.

Abstract: A propagating signal is propagated through a propagating medium to a plurality of receivers coupled to the propagating medium. A signal affected by a disturbance of the propagating medium is received. The received signal includes a signal portion that corresponds to the propagating signal that has been disturbed by the disturbance. At least a portion of a version of the signal portion of the received signal that corresponds to the propagating signal that has been disturbed by the disturbance is compared with one or more reference signal signatures of one or more disturbance types. Based at least in part on the comparison, it is determined that one of the one or more disturbance types corresponds to the disturbance of propagating medium.

Abstract: A method comprises cleaning a surface of a reticle by irradiating the surface of the reticle in a first exposure device for a predetermined irradiation time. A layout pattern of the reticle is projected onto a photo resist layer of a wafer in a second exposure device by an EUV radiation. The photo resist layer is developed to generate a photo resist pattern on the wafer. A surface of the wafer is imaged to generate an image of the photo resist pattern on the wafer. The generated image of the photo resist pattern is analyzed to determine critical dimension uniformity (CDU) of the photo resist pattern. The predetermined irradiation time is adjusted until the determined CDU satisfies a predetermined criterion.

Abstract: A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.

Abstract: A manufacturing method of a flip chip package structure is provided and has following steps: providing at least one silicon substrate having a connecting surface and at least one conductive base attached to the connecting surface; arranging a graphene copper layer covering the conductive base; laminating a photoresist layer on the connecting surface, etching the photoresist layer to form a cavity corresponding to the conductive base, and a portion of the graphene copper layer corresponding to the conductive base being exposed on a bottom of the cavity; electroplating a copper material on the graphene copper layer, and the copper material being accumulated in the cavity to form a copper pillar; removing the photoresist layer and the graphene copper layer covered by the photoresist layer.

Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.

Abstract: A device includes a first die, an interconnect structure, a RDL layer, a guard structure and an underfill layer. The interconnect structure is electrically connected to the first die. The RDL layer is disposed in a dielectric layer. The guard structure is disposed in the dielectric layer to define a connector region, wherein the guard structure and the interconnect structure are disposed on opposite sides of the die. The underfill layer surrounds the interconnect structure, the first die and the guard structure, wherein the underfill layer is kept outside of the connector region by the guard structure.

Abstract: A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.

Abstract: A method for extreme ultraviolet (EUV) lithography includes generating target droplets and using a first laser source to generate laser pulses to heat the target droplets to generate extreme ultraviolet (EUV) light and a plurality of particles. The method also includes using a supplemental laser source to generate laser pulses to ionize the plurality of particles, applying a magnetic field to direct ionized particles to debris collection device, and capturing the ionized particles by the debris collection device.

Abstract: A molding composition for a semiconductor package includes fillers, a resin, a hardener and a stress relaxation agent. The fillers are contained in an amount of 80% by weight to 90% by weight based on a total weight of the molding composition. The resin is contained in an amount of 1% by weight to 15% by weight based on a total weight of the molding composition. The hardener is contained in an amount of 1% by weight to 15% by weight based on a total weight of the molding composition. The stress relaxation agent is composed of silicone oil, and is contained in an amount of 0.5% by weight to 5% by weight based on a total weight of the molding composition.

Abstract: A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

Abstract: A package structure includes a package substrate, a package module on the package substrate, a thermal interface material (TIM) layer on the package module, and a package lid on the TIM layer. The package lid includes a package lid foot portion attached to the package substrate, and a package lid plate portion on the package lid foot portion and including a patterned bottom surface having a plurality of recessed portions, wherein at least a portion of the TIM layer is located in the plurality of recessed portions.

Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Abstract: A reticle enclosure includes a base including a first surface, a cover including a second surface and disposed on the base, wherein the base and the cover form an internal space therebetween that includes a reticle, and a layer of electrostatic discharge material disposed on the first surface, wherein the electrostatic discharge material reduces electrostatic charges on the reticle.

Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.