Abstract: The application relates to a method for developing the agitation system of a scale-up polymerization vessel. A simulated prediction model is obtained by use of a small polymerization vessel and by integrating Taguchi experimental design method with artificial intelligence (AI) neural network. Accordingly, vessel parameters for the agitation system of a scale-up polymerization vessel can be rapidly and accurately predicted based on simulation qualities thereof, further facilitating a construction of the agitation system of a scale-up polymerization vessel.

Abstract: A display device includes a display panel. The display panel has a functional display area. The functional display area includes a plurality of display pixels and a plurality of light transmitting regions. The plurality of display pixels are around by the plurality of the light transmitting regions. A boundary between one of the plurality of display pixels and one of the plurality of light transmitting regions comprises an arc segment.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A method performed by a BS for CHO is provided. The method includes transmitting a CHO command to a UE, the CHO command including a CHO command ID and a measurement ID associated with the CHO command ID; causing the UE to execute the CHO command to handover to a target BS when a trigger condition associated with the measurement ID is fulfilled; causing the UE to forgo transmitting the measurement report during the execution of the CHO command despite the UE being configured, via a report configuration associated with the measurement ID, to transmit the measurement report; transmitting, to the UE, a message that causes the UE to remove the CHO command; and after transmitting the message to the UE, determining that the report configuration is removed by the UE without transmitting, to the UE, an instruction to remove the report configuration.

Abstract: A signal to be used to propagate a propagating signal through a propagating medium with a touch input surface is sent. The propagating signal has been allowed to propagate through the propagating medium to a plurality of receivers coupled to the propagating medium. A received signal affected by a contact contacting the touch input surface is received. At least a portion of the received signal is compared with one or more reference signal signatures.

Abstract: A semiconductor structure includes a package, an electrical device and an underfill material. The package includes a redistribution structure and at least one die, and the at least one die is disposed on a first side of the redistribution structure. The electrical device is disposed on a second side of the redistribution structure, the electrical device has a top surface and a bottom surface opposite to each other, and the top surface faces the redistribution structure. The underfill material is disposed between the top surface and the redistribution structure and extending toward the bottom surface, the underfill material has an end surface corresponding to the bottom surface, and the end surface is a flat surface. In addition, a manufacturing method of the semiconductor structure is also provided.

Abstract: Provided are Chemical Mechanical Planarization (CMP) compositions that offer high and tunable Cu removal rates and low Cu static etching rates for polishing the broad bulk or advanced node copper or Through Silica Via (TSV). The CMP compositions also provide high selectivity of Cu film vs. other barrier layers, such as Ta, TaN, Ti, TiN, and SiN; and dielectric films, such as TEOS, low-k, and ultra-low-k films. The CMP polishing compositions comprise abrasive, oxidizer, at least two chelators selected from the group consisting of amino acids, amino acid derivatives, and combinations therefore; the Cu static etching reducing agents include, but not limited to, organic alkyl sulfonic acids with straight or branched alkyl chains, and salts of organic alkyl sulfonic acids.

Abstract: A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.

Abstract: A method of fabricating a semiconductor device includes providing a first substrate and forming a resist layer over the first substrate. In some embodiments, the method further includes performing an exposure process to the resist layer. The exposure process includes exposing the resist layer to a radiation source through an intervening mask. In some examples, the intervening mask includes a second substrate, a multi-layer structure formed over the second substrate, a capping layer formed over the multi-layer structure, and an absorber layer disposed over the capping layer. In some embodiments, the absorber layer includes a first main pattern area and an opening area spaced a distance from the first main pattern area. In various examples, the method further includes, after performing the exposure process, developing the exposed resist layer to form a patterned resist layer.

Abstract: An indicator identifying a force intensity of a touch input provided on a touch input surface is received. It is determined that the touch input is associated with an audio volume control. An audio volume is controlled based at least in part on the indicator identifying the force intensity of the touch input.

Abstract: A method includes rotating a wafer, dispensing a liquid from a center of the wafer to a peripheral edge of the wafer to control a temperature of the wafer, and etching an etch layer of the wafer with an etchant during or after dispensing the liquid. The liquid is dispensed through a nozzle.

Abstract: A package substrate structure includes a substrate, a metal base layer, a build-up film, a bonding layer, and a wiring unit. The metal base layer is disposed on the substrate. The build-up film is disposed on the metal base layer and is formed with trenches to expose the metal base layer. The build-up film includes an insulating material. The bonding layer is disposed on the build-up film and includes a graphene-metal composite. The graphene-metal composite includes a metal matrix, and a plurality of graphene nanostructures dispersed in the metal matrix and arranged among lattices of the metal matrix. The graphene nanostructures form covalent bonds with each other. The wiring unit is bonded to the build-up film through the bonding layer and fills the trenches so as to be electrically connected to the metal base layer. The wiring unit is formed with a wiring pattern on the build-up film.

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Abstract: A method includes rotating a wafer, dispensing a liquid from a center of the wafer to an edge of the wafer to control a temperature of the wafer, and etching an etch layer of the wafer with an etchant during or after dispensing the liquid. The liquid is dispensed through a nozzle.

Abstract: A method comprises cleaning a surface of a reticle by irradiating the surface of the reticle in a first exposure device for a predetermined irradiation time. A layout pattern of the reticle is projected onto a photo resist layer of a wafer in a second exposure device by an EUV radiation. The photo resist layer is developed to generate a photo resist pattern on the wafer. A surface of the wafer is imaged to generate an image of the photo resist pattern on the wafer. The generated image of the photo resist pattern is analyzed to determine critical dimension uniformity (CDU) of the photo resist pattern. The predetermined irradiation time is adjusted until the determined CDU satisfies a predetermined criterion.

Abstract: A manufacturing method of a flip chip package structure is provided and has following steps: providing at least one silicon substrate having a connecting surface and at least one conductive base attached to the connecting surface; arranging a graphene copper layer covering the conductive base; laminating a photoresist layer on the connecting surface, etching the photoresist layer to form a cavity corresponding to the conductive base, and a portion of the graphene copper layer corresponding to the conductive base being exposed on a bottom of the cavity; electroplating a copper material on the graphene copper layer, and the copper material being accumulated in the cavity to form a copper pillar; removing the photoresist layer and the graphene copper layer covered by the photoresist layer.

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Abstract: Polishing compositions comprising ceria coated silica particles and organic acids having one selected from the group consisting of sulfonic acid group, phosphonic acid group, pyridine compound, and combinations thereof, with pH between 5 and 10 and electrical conductivity between 0.2 and 10 millisiemens per centimeter provide very high silicon oxide removal rates for advanced semiconductor device manufacturing.