Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.

Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, a second encapsulant and a first RDL structure. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die. The first RDL structure is disposed on the bridge die and the second encapsulant.

Abstract: Copper chemical mechanical planarization (CMP) polishing formulation, method and system are disclosed. The CMP polishing formulation comprises abrasive particles of specific morphology and mean particle sizes (?100 nm, ?50 nm, ?40 nm, ?30 nm, or ?20 nm), at least two or more amino acids, oxidizer, corrosion inhibitor, and water.

Abstract: A signal to be used to propagate a propagating signal through a propagating medium with a touch input surface is sent. The propagating signal has been allowed to propagate through the propagating medium to a plurality of receivers coupled to the propagating medium. A received signal affected by a contact contacting the touch input surface is received. At least a portion of the received signal is compared with one or more reference signal signatures.

Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.

Abstract: A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.

Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Abstract: A physical disturbance sensor includes a plurality of piezoresistive elements configured in a resistive bridge configuration. A signal transmitter is electrically connected to the physical disturbance sensor and configured to send an encoded signal to the piezoresistive elements of the resistive bridge configuration. A signal receiver is electrically connected to the piezoresistive elements and configured to receive a signal from the physical disturbance sensor. The received signal from the physical disturbance sensor is correlated with the sent encoded signal in determining a measure of physical disturbance.

Abstract: A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

Abstract: Provided are Chemical Mechanical Planarization (CMP) formulations that offer high and tunable Cu removal rates and low copper dishing for the broad or advanced node copper or Through Silica Via (TSV). The CMP compositions provide high selectivity of Cu film vs. other barrier layers, such as Ta, TaN, Ti, and TiN, and dielectric films, such as TEOS, low-k, and ultra low-k films. The CMP polishing formulations comprise solvent, abrasive, at least three chelators selected from the group consisting of amino acids, amino acid derivatives, organic amine, and combinations therefor; wherein at least one chelator is an amino acid or an amino acid derivative. Additionally, organic quaternary ammonium salt, corrosion inhibitor, oxidizer, pH adjustor and biocide are used in the formulations.

Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, a second encapsulant and a first RDL structure. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die. The first RDL structure is disposed on the bridge die and the second encapsulant.

Abstract: A method of modulating growth factor responses of cells expressing C3a receptor (C3aR) and C5a receptor (C5aR) and at least one growth factor receptor includes administering to the cells at least one agent that modulates C3aR and/or C5aR signaling of the cells.

Abstract: A haptic feedback system is disclosed. The system includes a plurality of remote transmitters that are remote from a location of interest on a surface of the system. The system includes a signal generator that generates a signal for each of the remote transmitters. The remote transmitters propagate the signals through a medium of the surface and the signals interfere at the location of interest such that a localized disturbance is generated at the location of interest.

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Abstract: A sensor includes a plurality of piezoresistive elements and a plurality of electrical connection terminals. The plurality of piezoresistive elements are fabricated on a first side of a substrate. A second side of the substrate is configured to be coupled to an object where a physical disturbance is to be detected. A plurality of electrical connection terminals are coupled to the first side of the substrate.

Abstract: A signal to be used to propagate a propagating signal through a propagating medium with a touch input surface is sent. The propagating signal has been allowed to propagate through the propagating medium to a plurality of receivers coupled to the propagating medium. A received signal affected by a contact contacting the touch input surface is received. At least a portion of the received signal is compared with one or more reference signal signatures.

Abstract: The invention provides a manufacturing method for a multi-layer ceramic capacitor. the method includes: providing a plastic film; coating a layer of ceramic slurry on a side of the plastic film; coating a layer of copper paste on the layer of ceramic slurry to form a raw material, wherein the copper paste includes a copper powder and a graphene powder; and sintering the raw material at a temperature equal to or higher than 800° C. to sinter the layer of ceramic slurry into a ceramic dielectric layer and the copper paste into a copper electrode layer. The copper atoms are restricted by the graphene so that the copper atoms are confined in layer arrangement to improve flatness of copper atoms in the copper electrode layer.